Eduardo L. Rhod, Álisson Michels, Carlos A. L. Lisbôa, Luigi Carro ETS 2006

1. Conclusions • Experiments have shown that the proposed technique reduces the AVF up to 30 times. • The bad results for the 5-MR solution are due to the increased unprotected circuit area for voters, when compared to TMR. Future Work • Test the proposed approach with different case studies • Use this technique to implement a memory-based processor Porto Alegre - RS BRAZIL e-mail eduardo.rhod@ufrgs.br alisson.michels@ufrgs.br calisboa@inf.ufrgs.br carro@inf.ufrgs.br Fault Tolerance Against Multiple SEUs using Memory-Based Circuits to Improve the AVF Eduardo L. Rhod, Álisson Michels, Carlos A. L. Lisbôa, Luigi Carro ETS 2006 Technology trends for semiconductors forecast a higher incidence of soft errors caused by radiation in digital circuits implemented using sub 65nm technologies. New design approaches are necessary to generate circuits that are able to withstand multiple simultaneous upsets. Traditional fault tolerance approaches like TMR do not support multiple SEUs. Results show that even N-MR techniques do not work as expected. Several error detection and correction codes have been proposed, but most of them do not correct multiple bit flips, or when they do, the overhead in area and / or performance is not acceptable. Introduction Case Study: 4-tap, 8-bit FIR filter Memories using emerging technologies, like magnetic RAMs, are not affected by high energy particle strikes. This work proposes to replace parts of combinational circuits with intrinsically protected memories, thus reducing the overall architectural vulnerability factor (AVF), and, consequently, the soft error rate (SER). ROM MEMORY (COEFFICIENTS) 1 IN0 1 IN1 1 IN2 1 IN3 10 Replacing combinational circuits with memory 10 (the memory works as a truth table !) Example: 4x4-bit multiplier Combinational only Memory only + Circuit sensitive to faults REGISTER 10 10 11 8 inputs and 8 outputs 4 Memory y[17] ..... y[8] y[0] y[1] y[2] y[3] y[4] y[5] y[6] y[7] Input A 8 Result Results 4x4-bit Multiplier AVF and Timing for Single and Double Faults 4 Input B Total area = 2,048 transistors (considering 1 transistor per bit) Expensive !!! Total area = 304 transistors Case Study: 4x4-bit Multiplier 0 A0 A1 A2 A3 0 0 0 1) Column Multiplier B0 P6 P5 P4 P3 P2 P1 P0 Memory 0 0 A0 A1 A2 A3 0 0 B1 P7 FIR Filter AVF and Timing for Single and Double Faults 0 0 0 A0 A1 A2 A3 0 B2 Result Shift- Register Circuit sensitive to faults Register 0 0 0 0 A0 A1 A2 A3 Counter for mux selection signals B3 3 P3 P2 P1 P0 2) Line Multiplier A0 B0 B1 B2 B3 Memory A1 A2 A3 Circuit sensitive to faults P7 P6 P5 P4 Counter for mux selection signals Result Shift- Register 4 bit Register Universidade Federal do Rio Grande do Sul - UFRGS Programa de Pós-Graduação em Engenharia Elétrica Programa de Pós-Graduação em Computação http://www.ufrgs.br/ppgee, http://www.inf.ufrgs.br/pos/ppgc