Lecture 10 Interrupt System

1. Lecture 10Interrupt System Interrupt System

2. Lecture 10 - Interrupt In this lecture, we will study • Needs for interrupt • Principles of interrupt • Interrupt request structure • Interrupt preprocessing • Saving PC • Identifying source of interrupt • Calling interrupt processing routine • Interrupt major state • Interrupt processing routine • Priority interrupt Interrupt System

3. Why Interrupt ? • Power failure • Hardware failure • In the machine • On the communication line • Software problem • Attempt to unauthorized access to the protected area • Attempt to execute unauthorized codes • Try to execute an unrecognizable instruction • Operator • Input/Output • Need attention of CPU during I/O process • Need attention of CPU by the computer controlled environment Interrupt System

4. Principles of Interrupts • When there is an interrupt, continuation of the execution of the current program is meaningless • Execution of the Current program needs to be stopped • In a computer system, there are many sources of interrupts • Needs to prepare interrupt processing routines for each source of interrupts • Source of interrupt needs to be identified • Needs to initiate execution of the interrupt processing routine associated with the identified interrupt • When the interrupt is resolved, the interrupted program needs to be continued for the efficiency reason • Needs to resume execution of the interrupted program Interrupt System

5. Principle Of Interrupt Interrupt process [1] Program ceases to execute, When ? • At the completion of the current instruction • Not at the end of current memory(machine) cycle [2] Save PC, Where ? • Stack, Memory [3] Execute interrupt preprocessing • Identify the source of interrupt • Initiate the execution of the Interrupt Processing Routine of the identified interrupt source [4] Execution of the interrupt processing routine • Save the state of the interrupted program, Where ? • Resolve the interrupt [5] Restore PC and the status of the interrupted program, and resume execution of the interrupted program Interrupt System

6. Interrupt Request Line CPU . . . Interrupt Resource Interrupt Resource CPU . . . Interrupt Resource Interrupt Resource Interrupt Resource Interrupt Resource ... CPU Interrupt Resource Interrupt Resource ... Interrupt Request Single Line Interrupt Request Multiple Line Interrupt Request Mixed Interrupt Request Interrupt System

7. Interrupt Enable Line Polling Line Interrupt Request Line IE RI set RI Interrupt Dev Decoder Interrupt Dev Decoder IRQ DIR IRQ DIR reset . . . IRQ DIR SEL SEL CPU Interrupt Recognition Line Interrupt 0 Interrupt 1 Single Line Interrupt Request Interrupt System

8. Interrupt Recognition Line Interrupt Enable Line IE Interrupt Request Line set DIR IRQ . . . IRQ DIR IRQ DIR set RI Interrupt Request Line Interrupt Recognition Line CPU Interrupt 0 . . . Interrupt (n-1) Multiple Line Interrupt Request Interrupt System

9. Time Out • 아침을 먹으려고 커피숖에 가서 이것 저것 쟁반에 담고, 계란 요리를 해주는 카운터에 도달하여 차례를 기다렸다. • 그런데 계란 요리사의 표정을 보니 매우 우울해 보였다. • 마침내 차례가 되어 계란 두 개를 부탁하였다. • 요리사가 물었다. “어떻게 해 드릴까요?” • 요리사가 측은하게 생각되어 편하게 해 줄 생각으로 말했다. “자네가 편한 대로 해 주게.” • 그 말이 떨어지자마자 그는 계란 두 개를 집어서 쟁반 위에 깨뜨려 주었다. Interrupt System

10. Interrupt Preprocessing • Save PC • Main memory location 0 • Interrupt Vector(IV) • Identify the source of interrupt • Software(Polling) • Hardware • Initiate execution of the Interrupt Processing Routine(IPR) These functions can be implemented in one Interrupt Preprocessing Routine(IPPR) Interrupt System

11. Interrupt Request PC 74 IPPR [1] M[0] PC; [2] PC 1, FETCH; JMP IPPR [1] SP SP + 1; [2] S[SP] PC; 1. Save interrupted program state 2. Identify the source of interrupt 3. Initiate IPR Interrupt Vector IVA+0 IVA+1x2 IVA+2x2 (PC save area) JMP IPR (PC save area) JMP IPR Interrupt source is identified with HW [1] IV[IVA+INx2] PC; [2] PC IVA+INx2+1, FETCH; (PC save area) JMP IPR . . . Saving PC • Memory Location 0 • Stack • Interrupt Vector 0 1 73 74 230 Running Program Interrupt System

12. Interrupt Req RI=1 and IE=1 Interrupt 0 SEL=1 ? y Interrupt 0 recognized y Interrupt 1 SEL=1 ? Interrupt 1 recognized ... Interrupt n SEL=1 ? y Interrupt n recognized No Interrupt Identifying Source of Interrupt:Software Polling Interrupt System

13. Interrupt Enable Line IE RI 1 ... Interrupt Select Line Interrupt Request Line Interrupt Dev. Code Generator Interrupt Dev. Code Generator IRQ DIR IRQ DIR SEL SEL CPU Interrupt Dev. Code Line Interrupt 0 Interrupt 1 . . . Identifying Source of Interrupt:Hardware No interrupt if Daisy Chain returns 1 Daisy Chain IRQ Interrupt System

14. CALL X M[X] PC, PC X+1; CALL @X M[M[X]] PC, PC M[M[X]]+1; X0 X1 Xn Interrupt Preprocessing Routine … CALL @(DISP + IN) … DISP: X0 X1 … Xn IPR 0: Interrupt 0 processing ... IPR 1: Interrupt 1 processing … . . . IPR n: Interrupt n processing Calling Interrupt Processing Routine Interrupt System

15. INT.t0: MAR 0, W; INT.t1: MBR PC; INT.t2: PC 1; /Branch to Int Preproc Routine INT.t3: FET; INT.t0: MAR (IVA+INx2), W; INT.t1: MBR PC; INT.t2: PC (IVA+INx2+1); /Branch to Int. Proc Routine INT.t3: FET; Interrupt Major State Save PC in Location 0 Interrupt Vector Interrupt System

16. Interrupt Processing [1] Saving interrupted program status to be used for restoring status when the program resumes execution after the interrupt processing • Special location in memory • Stack • Registers [2] Selective interrupt disable • Interrupt mask [3] Interrupt processing [4] Restoration of the status and prepare to begin execution of the interrupted program Interrupt System

17. Saving Program Status • IPR saves in the area within IPR • Special Stack • Assign separate register set to each interrupt processing routine Interrupt System

18. Interrupt Mask Line IE RI MASK k Interrupt Enable Line Interrupt Dev.Code Line Interrupt Request Line Interrupt Dev Code Decoder Interrupt Dev Code Decoder IR D IR D SEL SEL CPU Interrupt Recognition Line Interrupt 0 Interrupt 1 . . . Direct clear input of the FF Selective Interrupt Disable Interrupt System

19. Priority Interrupt • Software Priority - Polling • Polling order is the interrupt priority • Low cost • Interrupt processing routine can be interrupted by any interrupt • In order to establish priority, interrupt mask can be used to mask out the lower priority interrupts • This establishes 3-level priority • Unmasked interrupts are higher priority than the current interrupt • Currently processing interrupt • Masked interrupts are lower priority than the current interrupt • Hardware Priority Interrupt System

20. Priority level RI 0 1 2 3 . . . n-1 If RI(k) = RI(h) = 1, and k < h Priority of Interrupt k is higher than Interrupt h (2) PR=k>0 and RI = 0, i.e., there are pending interrupts If an interrupt is received Highest priority among pending interrupts h = Min { i } RI(i)=1 If h>k, continue processing k, If h<k, Interrupt IPR k and process h; PR=h Priority Interrupt - Hardware PR: Current Interrupt Priority Level(PR<0, when there is no interrupt being processed) (1) PR<0 and RI=0, i.e., no pending interrupt If an interrupt request is received Interrupt to be processed h = Min { i } RI(i)=1 Process the requested interrupt; PR = h Interrupt System