Chapter 3

1. Chapter 3 • The concept of the signal • Process concurrency • Delta time • Concurrent and sequential statements • Process activation by a signal event • Signal-valued & signal-related attributes • Exercises EE514

2. The concept of the signal • Signal functions as connection line which transfers information between circuit parts • Signal properties • present and future values • timing delay • event and transaction • signal driver and signal resolution • Multiple drivers EE514

3. NANXOR code entity NANDXOR is port ( A, B : in bit; C : in bit; D : out bit); end NANDXOR; architecture RTL of NANDXOR is signal T : bit; begin p0 : T <= A nand B after 2 ns; p1 : process (T, C) begin D <= T xor C after 3 ns; end process p1; end RTL; Process concurrency EE514

4. Process concurrency Signal T:bit; Defines T as the connection signal between NAND and OR gates. Initialization: signals set to their default (left most for their type) values Each process is evaluated and then suspended Active Suspended Update signal value Signal event Select a process by a scheduler Execution complete Running EE514

5. Process concurrency architecture RTL of NANDXOR is signal T : bit; begin p0 : T <= A nand B after 2 ns; p1 : process (T, C) begin D <= T xor C after 3 ns; end process p1; end RTL; EE514

6. Delta time architecture DELTA of NANDXOR is signal T : bit; begin p0 : T <= A nand B; p1 : process (T, C) begin D <= T xor C; end process p1; end DELTA; EE514

7. Delta time • Compare Figures 3.5 & 3.6 EE514

8. Delta time • Waveforms at time 30 EE514

9. Delta time Delta time Processes p0, p1 have no time delay, but if the simulator continues to increase the delta delay, the delta goes up infinitely and the simulator may go into an infinite loop. EE514

10. Concurrent statements Sequential statements if statement case and loop statements procedure call statement assert statement signal assignment statement variable assignment statement null, exit, and wait statements return and next statements Concurrent & sequential statements block statement process statement generate statement procedure call statement assert statement signal assignment component instantiation EE514

11. Concurrent & sequential statements VHDL coding rules • Only concurrent statements can be inside the architecture statement part. • Sequential statements can only appear inside the procedure and function body and inside the process statement. • Signals are used to communicate among concurrent processes. • Local variables can only be declared inside the procedure and function body and the process statement. They are notvisible outside of the procedure, function, and process statement. EE514

12. Concurrent & sequential statements • Architecture VHDL code entity OVERALL is end OVERALL architecture RTL of OVERALL is --architecture declarative part begin --architecture statement part end RTL; EE514

13. Concurrent & sequential statements EE514

14. Process activation by a signal event architecture SLIST of NANDXOR is signal T : bit; begin p0 : T <= A nand B; p1 : process (T) begin D <= T xor C; end process p1; end SLIST; EE514

15. Process activation by a signal event T is the sensitivity list of the p1 process (line 5 of SLIST architecture). Process is activated by a signal T event. A process statement requires an explicit wait statement or a process sensitivity list but not both. EE514

16. Process activation by a signal event Wrong simulation waveforms of the SLIST EE514

17. Signal-valued & signal-related attributes • SIG’delayed(T) defines a signal which is the signal SIG delayed by time T. T=0 ns is the default if parameter T is not specified. • SIG’stable(T) defines a BOOLEAN signal whose value is TRUE if signal SIG has not had an event for the length of time T. T=0 ns is the default if parameter T is not specified. SIG’stable would be FALSE during the simulation cycle when SIG is changed and then returns to TRUE. EE514

18. Signal-valued & signal-related attributes • SIG’quiet(T) defines a BOOLEAN signal whose value is TRUE if signal SIG has not had an transaction (not active) for the length of time T. T=0 ns is the default. SIG’quiet would be FALSE during the simulation cycle when SIG is assigned to and then returns to TRUE. • SIG’transaction defines a BIT signal whose value toggles each time a transaction occurs on signal SIG. EE514

19. Signal-valued & signal-related attributes • SIG’event is a BOOLEAN typed attribute. It is true if an event occurs on signal SIG during the current simulation cycle. • SIG’active is a BOOLEAN typed attribute. It is true if a tranction occurs on signal SIG during the current simulation cycle. • SIG’last_event is a TIME typed attribute. It returns the amount of time elapsed since the last event on signal SIG. EE514

20. Signal-valued & signal-related attributes • SIG’last_active is a TIME typed attribute.It returns the amount of time elapsed since the last transaction on signal SIG. • SIG’last_value returns the value of signal SIG before the last event on signal SIG. EE514

21. entity RUNAWAY is port ( X : in bit; Z : out bit); end RUNAWAY; Exercises Is it possible for a VHDL simulator to run forever without advancing simulation time? For example, Figure 3.13 shows a NAND gate with its output connecting to one of its inputs architecture RTL of RUNAWAY is signal T : bit; begin T <= X nand T; Z <= T; end RTL; EE514