ECE-C662 Lecture 2 Prawat Nagvajara

1. ECE-C662 Lecture 2Prawat Nagvajara • Design flow • Simulation and verification • RTL and behavioral design • Behavioral compiler • Design flow • Representation • Allocation • Netlisting • Control FSM • Compiler outputs

2. Control synthesis Dataflow synthesis Design flow Behavioral synthesis RTL synthesis Logic synthesis

3. Domain-Specific Synthesis • Dataflow oriented synthesis • Input data are streams of samples • Operations on data are stream oriented • Signal flow diagrams, e.g., x = axz-1 + bu or x[k] = ax[k-1] + bu[k] • Signal processing applications, e.g., filtering, modulations, etc. • Languages and schematic capture editors available • Outputs are HDL description to behavioral or RTL synthesis tool

4. Control floworiented synthesis • Finite state machines • States and their transitions • Input data are conditions • Hierarchical descriptions • Languages and schematic capture editors available • Outputs are HDL description to behavioral or RTL synthesis tool

5. Behavioral Synthesis • Back end for control flow and dataflow synthesis with HDL interchange format • Language-based general purpose tool • Languages: Verilog, VHDL, C, APL, ISP • Scheduling is the core activity • Create states and assign operations to states • Allocation • Operations assign to hardware and data to storage elements • Trade off latency for area and register area for combinational and interconnect area • Optimized design advantages over RTL synthesis

6. RTL Synthesis • State graph; states and transitions are tightly bound to resources • Serve as a back end for other synthesis (but it can be a front-end tool in its own right) • Cumbersome, verbose and error prone Logic synthesis • Propagation delay and area optimization • Back end for higher abstraction

7. Simulation and Verification • Simulation tests the response for particular inputs • Formal verification mathematically proves equivalence between the design and a ‘golden’ model described by math properties • E.g., a design is deadlock free, against Boolean expressions and specific functions • Design verification checks properties • Implementation verification checks, e.g., an optimized version against un-optimized version • They work well with combinational logic but the problem is very difficult for design with states, e.g., under process statements

8. RTL and Behavioral Design • Behavioral synthesis tools glue the domain-specific and RTL synthesis tools, e.g., C description to the dataflow oriented toolx=0;while (!reset) { u = read(input); x = a*x + b*u; write(output);} • Initial questions on data widths, operation ordering, rounding methods, timing, states and queue sizes are abstracts in terms of C or C++ • This abstract model is translated to HDL model where interfaces and timing between modules are corrected using simulation

9. RTL and Behavioral Design continued • Synthesizable description • Processes are synthesized into separate FSMs or logic blocks. They may be connected by logic blocks. • The number of states in behavioral synthesis can be optimized and operations assigned to states can also changes post optimization • In RTL synthesis, the design decide on the FSM design

10. a x1 * := b u Schedule example: X[k] = ax[k-1] + bu[k] * + x <=

11. a x1 mux * u b * Alocation: X[k] = ax[k-1] + bu[k] R * + + x

12. Behavioral Compiler Flow • HDL input: simulate 1. HDL analysis (parsing and semantic analysis) and elaboration for scheduling 2. User constraints • Timing model of the dataflow portion • Explicit user constraints, e.g., number of clock cycles • Dataflow -> gate-level netlist -> target technology • Early timing analysis (technology-specific scheduling) 3. Schedule • Assignment of operations to states

13. Behavioral Compiler Flow Continued 4. Allocate • Modules and registers are constructed • Mapping from the logical operations and data to netlist modules and registers • Outputs a logical description of the datapath-abstract resources and data transfer 5. Build netlist and control FSM • Simulation 6. Logic-level optimization; constraints and report • Timing-accurate timing simulation, testability assertion, test generation and layout • EDIF or others output

14. FIR Filter Project • Initial design • C code or Mathlab code • FIR filter has 17 tapsy[k] = h[0]u[k] + … + h[L]u[k-L] library ieee; Use ieee.std_logic_1164.all, ieee.std_logic_arith.all; Package coeffs is type coef_arr is array (0 to 16)of signed (8 downto 0); Constant coeffs: coef_arr := coef’( “111111001”, “111111011”,…,”111111001”); End coeffs;

15. library ieee; Use ieee.std_logic_1164.all, ieee.std_logic_arith.all, work.coeffs.all; Entity fir is Port(ck,reset: in std_logic; sample : in signed(7 downto 0); result : out signed(9 downto 0)); End fir;

16. IIR Filter Project y[k] = a1y[k-1] + a2y[k-2] + b0u[k] + b1u[k-1] + b2u[k-2]