ASICs vs. FPGAs

1. ECE 448 Lecture 15 ASICs vs. FPGAs ECE 448 – FPGA and ASIC Design with VHDL

2. FPGAs vs. ASICs FPGAs ASICs Off-the-shelf High performance Low development costs Low power Short time to the market Low cost (but only in high volumes) Reconfigurability ECE 448 – FPGA and ASIC Design with VHDL

3. ASIC Design Example – Factoring circuit/GMU Global Memory Local Memory ECE 448 – FPGA and ASIC Design with VHDL

4. ASIC 130 nm vs. Virtex II 6000 Factoring/GMU 19.80 mm 51x Area of Xilinx Virtex II 6000 FPGA (estimation by R.J. Lim Fong, MS Thesis, VPI, 2004) 19.68 mm 2.7 mm 2.82 mm Area of an ASIC with equivalent functionality ECE 448 – FPGA and ASIC Design with VHDL

5. ASICs vs. FPGAs Source: I. Kuon, J. Rose, University of Toronto “Measuring the Gap Between FPGAs and ASICs” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 62, no. 2, Feb 2007. ECE 448 – FPGA and ASIC Design with VHDL

6. ASICs vs. FPGAs 23 representative circuits implemented using FPGAs and ASICs - computer arithmetic (booth, cordic18, cordic8, etc.) - digital signal processing (rs_encoder, fir3, fir24, etc.) - communications (ethernet, mac1, atm, etc.) - cryptography (des_area, des_perf, aes, aes192, etc.) - scientific computations (molecular, raytracer, etc.) ECE 448 – FPGA and ASIC Design with VHDL

7. ECE 448 – FPGA and ASIC Design with VHDL

8. ECE 448 – FPGA and ASIC Design with VHDL

9. ECE 448 – FPGA and ASIC Design with VHDL

10. ECE 448 – FPGA and ASIC Design with VHDL

11. ASIC Design Flow Reference Implementation Algorithm Specification C, C++ RTL Design DesignQuality test vectors Verilog, VHDL Synopsys Design Compiler VCS latencythroughput(post-synthesis) Logic Synthesis Simulation stdcell lib Hercules Calibre Synopsys IC Compiler Cadence Encounter die areapin count Layout LVS process lib Mentor Calibre Synopsys StarRCXT VCD latencythroughput (post P&R) Simulation Parasitic Extraction PrimeTime power diss

12. Simplified ASIC Design Flow Synthesis Front-End Design Timing Analysis Floorplanning Back-End Design Placement Clock Tree Synthesis Routing Design for Manufacturing 31 ECE 448 – FPGA and ASIC Design with VHDL

13. Major ASIC Toolsets Cadence Magma ECE 448 – FPGA and ASIC Design with VHDL

14. Simplified ASIC Design Flow Synopsys Tools Synthesis Design Compiler Front-End Design Primetime Timing Analysis Floorplanning Back-End Design Placement Astro Clock Tree Synthesis Routing Design for Manufacturing 31 ECE 448 – FPGA and ASIC Design with VHDL

15. A Complete Placed and Routed Chip IP 28 ECE 448 – FPGA and ASIC Design with VHDL

16. Digital system design technologies coverage in the CpE & EE programs at GMU ASICs Microprocessors FPGAs Computer Organization ECE 445 ECE 447 ECE 431 Digital Circuit Design Single Chip Microcomputers ECE 448 FPGA and ASIC Design with VHDL ECE 545 Digital System Design with VHDL ECE 511ECE 611 ECE 645 Microprocessors Computer Arithmetic Digital Integrated Circuits Advanced Microprocessors ECE 586 ECE 681 VLSI Design for ASICs

17. DIGITAL SYSTEMS DESIGN 1. ECE 545 Digital System Design with VHDL– K. Gaj, project, FPGA design with VHDL, Aldec/Xilinx/Altera 2. ECE 645 Computer Arithmetic– K. Gaj, project, FPGA design with VHDL or Verilog, Aldec/Xilinx/Altera/Synopsys 3. ECE 586 Digital Integrated Circuits – D. Ioannou 4. ECE 681 VLSI Design for ASICs– N. Klimavicz, project/lab, front-end and back-end ASIC design with Synopsys tools 5. ECE 682 VLSI Test Concepts– T. Storey, homework