VLSI System Design

1. VLSI System Design Lect. 2.2 CMOS Transistor Theory2 Engr. Anees ul Husnain ( anees.buzdar@gmail.com ) Department of Electronics & Computer Systems Engineering, College of Engineering & Technology, IUB

2. Outline . . . • Non-ideal Transistor Behavior • High Field Effects • Mobility Degradation • Velocity Saturation • Channel Length Modulation

3. Ideal Transistor I-V for pMOS for nMOS The important practical effects are neglected. . .

4. Ideal vs. non-ideal Non-ideal ideal • Saturation current does not increase quadratically with Vgs • Saturation current lightly increases with increase in Vds

5. R E A S O N S • Velocity Saturation • Mobility Degradation • Channel Length Modulation • Sub-Threshold Conduction • Junction Leakage

6. Ideal vs. non-ideal • There is leakage current when the transistor is in cut off • Ids depends on the temperature

7. Ideal vs. Simulated nMOS I-V Plot • 65 nm IBM process, VDD = 1.0 V

8. ON and OFF Current • Ion = Ids @ Vgs = Vds = VDD • Saturation • Ioff = Ids @ Vgs = 0, Vds = VDD • Cutoff

9. Electric Fields Effects • Vertical electric field: Evert = Vgs / tox • Attracts carriers into channel • Long channel: Qchannel Evert • Lateral electric field: Elat = Vds / L • Accelerates carriers from drain to source • Long channel: v = mElat

10. Coffee Cart Analogy • Tired student runs from VLSI lab to coffee cart • Freshmen are pouring out of the some other lecture • Vds is how long you have been up • Your velocity = fatigue × mobility • Vgs is a wind blowing you against the glass (SiO2) wall • At high Vgs, you are buffeted against the wall • Mobility degradation • At high Vds, you scatter off freshmen, fall down, get up • Velocity saturation • Don’t confuse this with the saturation region

11. Velocity Saturation • When A strong enough electric field is applied: • the carrier velocity in the semiconductor reaches a maximum value saturation velocity • the carriers lose energy through increased levels of interaction with the lattice, collisions and by emitting phonons

12. Velocity Saturation

13. Velocity Saturation

14. Velocity Saturation

15. Velocity Saturation • At high Elat, carrier velocity rolls off • Carriers scatter off atoms in silicon lattice • Velocity reaches vsat • Electrons: 107 cm/s • Holes: 8 x 106 cm/s • Better model

16. Vel Sat I-V Effects • Ideal transistor ON current increases with VDD2 • Velocity-saturated ON current increases with VDD • Real transistors are partially velocity saturated • Approximate with a-power law model • Ids VDDa • 1 < a < 2 determined empirically (≈ 1.3 for 65 nm)

17. Alpha model • Transistor to operate in region: (moderate supply voltages) • v no longer inc. with field but not completely saturated • a – velocity saturation index For the Transistors with • Long channels or Low Vdd  quadratic I-V characteristics in saturation  Alpha = 2 (max) • More velocity saturated  increasing Vgs less effect on current  Alpha decreases (reaching 1 for completely velocity saturated) • Simply THE MODEL HAS STRAIGHT LINE IN LINEAR REGION

18. Alpha model Pc, Pv and alpha are found by fitting the model to the empirical modeling results

19. Empirical Modeling • Refers to any kind of (computer) modelling based on empirical observations rather than on mathematically describable relationships of the system modelled. • The word empirical denotes information gained by means of observation, experience, or experiment

20. Channel Length Modulation • Reverse-biased p-n junctions form a depletion region • Region between n and p with no carriers • Width of depletion Ld region grows with reverse bias • Leff = L – Ld • Shorter Leff gives more current • Idsincreases with Vds • Even in saturation

21. Increasing Vds • increases depletion width • decreases effective channel length • increases current Channel length modulation factor (empirical factor) Channel length modulation

22. Next . . . • Threshold Voltage Effects • Body Effect • Drain-Induced Barrier Lowering • Short Channel Effect • Leakage • Subthreshold Leakage • Gate Leakage • Junction Leakage • Process and Environmental Variations

23. Threshold Voltage Effects • Vt is Vgs for which when the channel starts to invert • Means Vgs has the control of thresh hold • Ideal models assumed Vt is constant • Really depends (weakly) on almost everything else: • Body voltage: Body Effect • Drain voltage: Drain-Induced Barrier Lowering • Channel length: Short Channel Effect

24. Body Effect • Body is a fourth transistor terminal • Vsb affects the charge required to invert the channel • Increasing Vs or decreasing Vb increases Vt • fs = surface potential at threshold • Depends on doping level NA • And intrinsic carrier concentration ni • g = body effect coefficient

25. DIBL • Electric field from drain affects channel • More pronounced in small transistors where the drain is closer to the channel • Drain-Induced Barrier Lowering • Drain voltage also affect Vt • High drain voltage causes current to increase.

26. Short Channel Effect • In small transistors, source/drain depletion regions extend into the channel • Impacts the amount of charge required to invert the channel • And thus makes Vt a function of channel length • Short channel effect: Vt increases with L • Some processes exhibit a reverse short channel effect in which Vt decreases with L

27. Leakage • What about current in cutoff? • Simulated results • What differs? • Current doesn’t go to 0 in cutoff

28. Tunnel current polysilicon gate W t ox L n+ n+ p-type body Subthreshold conduction Junction leakage Leakage Sources • Subthreshold conduction • Transistors can’t abruptly turn ON or OFF • Dominant source in contemporary transistors • Gate leakage • Tunneling through ultrathin gate dielectric • Junction leakage • Reverse-biased PN junction diode current • Subthreshold leakage is the biggest source in modern transistors

29. Junction Leakage • Reverse-biased p-n junctions have some leakage

30. Leakage current: junction leakage and tunneling • Junction leakage: reverse-biased p-n junctions have some leakage. • Is depends on doping levels and area and perimeter of diffusion regions • Tunneling leakage: • Carriers may tunnel thorough very thin gate oxides • Negligible for older processes

31. Temperature Sensitivity • Increasing temperature • Reduces mobility • Reduces Vt • IONdecreases with temperature • IOFFincreases with temperature

32. Process variations threshold voltage 0.97V threshold voltage 0.57V Both MOSFETs have 30nm channel with 130 dopant atoms in the channel depletion region Process variations impact gate length, threshold voltage, and oxide thickness

33. So What? • So what if transistors are not ideal? • They still behave like switches. • But these effects matter for… • Supply voltage choice • Logical effort • Quiescent power consumption • Pass transistors • Temperature of operation