EDK Lab for PowerPC and MicroBlaze

1. EDK Lab for PowerPC and MicroBlaze Paul Glover, Winnie HsuGlobal Services Division

2. Agenda • Introduction (30min) • Embedded System Tools Overview • Labs (90min) • Lab1(a) Intro to EDK Flow - PowerPC Track • Lab1(b) Intro to EDK Flow - MicroBlaze Track • Lab2 Web Server Design Example (Optional) • Lab3 Using SGP as MHS Editor (Preview) “Xilinx Confidential”

3. EDK Glossary Tools • EDK = Embedded development Kit. • PlatGen = Platform generator. Uses MHS file to create an implementation netlist of a bus-based subsystem. • LibGen = Library generator. Uses MHS/MSS files, SW libraries and source files to generate executable images. • SimGen = Simulation generator. Uses MHS/MVS files to configure and generate simulation related package including simulation models, HDL wrappers, script, etc. • XMD = Xilinx Microprocessor Debug Platform Specification Format (PSF) • MHS = Microprocessor Hardware Specification. • MSS = Microprocessor Software Specification. • MVS = Microprocessor Verification Specification. • MPD = Microprocessor Peripheral Description. • PAO = Peripheral Analyze Order • BBD= Black-Box Definition • MDD = Microprocessor Driver Description. “Xilinx Confidential”

4. Embedded Development Flow • Embedded System Design Consists of • Hardware design • Software design • HW / SW co-verification (Simulation & Debug) • Xilinx Platform Studio (XPS) • Provides project management interfaces • Coordinates tool elements with well defined interfaces XPS Hardware Design Simulation HW-SW Partitioning HW-SW Co-Verification Debug Software Design “Xilinx Confidential”

5. Embedded Development Flow • Embedded System Design Consists of • Hardware design • Software design • HW / SW co-verification (Simulation & Debug) XPS Hardware Design Simulation HW-SW Partitioning HW-SW Co-Verification Debug Software Design “Xilinx Confidential”

6. PLB EMC OPB GPIO JTAG CNTL PPC405 PLB / Arbiter PLB2OPB Bridge OPB / Arbiter OPB2PLB Bridge PLB BRAM I/F BRAM Block OPB UART Hardware Flow HW Development Flow • MHS • Microprocessor Hardware Specification • A template that describes hardware structure • PlatGen • Uses MHS file to create the hardware platform 1. Specify Processor, Bus & Peripherals MHS HW Configuration 2. Automatic Hardware Platform Generation PlatGen Xflow / ProjNav 3. Xilinx Implementation Flow Bitstream Download to FPGA “Xilinx Confidential”

7. Example MHS Format # Global Ports PARAMETER VERSION = 2.0.0 PORT sys_clk = sys_clk, DIR=INPUT PORT system_reset = system_reset, DIR=INPUT PORT leds = leds, DIR = INOUT, VEC = [0:7] ... BEGIN plb_v34 PARAMETER HW_VER = 1.01.a PARAMETER INSTANCE = myplb PORT PLB_Clk = sys_clk PORT SYS_Rst = sys_bus_reset PARAMETER C_DCR_INTFCE = 0 END BEGIN plb2opb_bridge PARAMETER INSTANCE = myplb2opb PARAMETER C_RNG0_BASEADDR = 0xA0000000 PARAMETER C_RNG0_HIGHADDR = 0xA03FFFFF BUS_INTERFACE SPLB = myplb BUS_INTERFACE MOPB= myopb ... BEGIN ppc405 PARAMETER INSTANCE = PPC405_i PARAMETER HW_VER = 1.00.a BUS_INTERFACE IPLB = myplb BUS_INTERFACE DPLB = myplb PORT CPMC405CLOCK = sys_clk PORT PLBCLK = sys_clk PORT CPMC405CORECLKINACTIVE = net_gnd …. FFFFFFFF PLB BRAM PPC405 FFFF8000 … … PLB OPB GPIO A0000000 PLB BRAM PLB2OPB Bridge A00001FF … … “Xilinx Confidential”

8. How to Create an MHS? • XPS GUI • Generate MHS Template • Fill in the connections in the editor • * SysGenPro • Block-like Entry * This new feature in SGP-beta has not been completed yet. ! LAB1 LAB3 “Xilinx Confidential”

9. What Does PlatGen Do? • PlatGen Generates • HDL wrappers • NGC(s) • BMM File, to initialize BRAMs in the later steps • Synthesis scripts / project file HW Development Flow MPD & others MPD PAO BDD MPD PAO BDD 1. Specify Processor, Bus & Peripherals MHS File Processor(s) MHS HW Configuration MPD & others MPD PAO BDD 2. Automatic Hardware Platform Generation MPD PAO BDD PlatGen PlatGen Processor IP(s) Xflow/ ISE NPL 3. Xilinx Implementation Flow MPD & others MPD PAO BDD MPD PAO BDD HDL Wrappers, NGC, BMM, Synth SCR/PRJ, Bitstream MYIP and Logic Download to FPGA “Xilinx Confidential”

10. PLB EMC OPB GPIO JTAG CNTL PPC405 PLB / Arbiter PLB2OPB Bridge OPB / Arbiter OPB2PLB Bridge PLB BRAM I/F BRAM Block OPB UART Q: How to Add My Peripheral? • Design Processor Peripherals • Understand common bus protocols (OPB / PLB / DCR) • Understand logic elements you need (addr decode, regs, etc..) • Understand PlatGen supported signals and generics • Incorporate into PlatGen Flow • Create MPD,PAO, BBD (if applicable) • Search path • Directory tree ? “Xilinx Confidential”

11. PLB EMC OPB GPIO JTAG CNTL PPC405 PLB / Arbiter PLB2OPB Bridge OPB / Arbiter OPB2PLB Bridge PLB BRAM I/F BRAM Block OPB UART Q: How to Export the System into a Larger Design? XPS Exports a Project Navigator Project (NPL) File LAB1 ? “Xilinx Confidential”

12. Embedded Development Flow • Embedded System Design Consists of • Hardware design • Software design • HW / SW co-verification (Simulation & Debug) XPS Hardware Design Simulation HW-SW Partitioning HW-SW Co-Verification Debug Software Design “Xilinx Confidential”

13. Software Flow PLB EMC OPB GPIO JTAG CNTL PPC405 PLB / Arbiter PLB2OPB Bridge OPB / Arbiter OPB2PLB Bridge PLB BRAM I/F BRAM Block OPB UART • MHS • Microprocessor Software Specification • LibGen • Customizes libraries, drivers etc. • Data2BRAM • Update Bitstream with program/data information SW Development Flow 1. Specify Software Architecture SW Configuration MHS 2. Automatic Software BSP/Library Generation LibGen GNU (MB&PPC) Diab(PPC) Compilers 3. Software Compilation Hardware Flow Executable Executable in on-chip memory Executable in off-chip memory Data2BRAM ? Bitstream GDB / XMD Download to Board Download to FPGA “Xilinx Confidential”

14. Example MSS Format PARAMETER VERSION = 2.0.0 PARAMETER HW_SPEC_FILE = system.mhs BEGIN PROCESSOR PARAMETER HW_INSTANCE = my_microblaze PARAMETER DRIVER_NAME = cpu PARAMETER DRIVER_VER = 1.00.a PARAMETER EXECUTABLE = executable.elf PARAMETER COMPILER = mb-gcc PARAMETER ARCHIVER = mb-ar PARAMETER DEBUG_PERIPHERAL = my_jtaguart PARAMETER BOOT_PERIPHERAL = my_jtaguart PARAMETER STDIN = my_uartlite PARAMETER STDOUT = my_uartlite ... END BEGIN DRIVER PARAMETER HW_INSTANCE = myethernet PARAMETER DRIVER_NAME = emac PARAMETER DRIVER_VER = 1.00.b PARAMERER LEVEL = 0 PARAMETER LIBRARY = XilNet END OPB JTAG UART OPB UART LITE OPB / Arbiter MicroBlaze BEGIN DRIVER PARAMETER HW_INSTANCE = my_uartlite PARAMETER DRIVER_NAME = uartlite PARAMETER DRIVER_VER = 1.00.b PARAMERER LEVEL = 0 END OPB GPIO LM OPB BRAM I/F BRAM Block “Xilinx Confidential”

15. How to Create an MSS? • Identifies driver for selected processor • Identify STDIO for selected processor • Identify debug/boot peripherals ( MB only) MicroBlaze Only “Xilinx Confidential”

16. How to Create an MSS? • Identifies ISR for selected peripheral • Identifies driver for selected peripheral “Xilinx Confidential”

17. What Does LibGen Do? • LibGen Generates and Configures • Include file, such as xparameters.h • libc.a, libm.a, libxil.a libraries MHS File SW Development Flow PowerPC BSP / MicroBlaze BSP MSS File 1. Specify Software Architecture MHS SW Configuration LibGen 2. Automatic Software BSP/Library Generation LibGen Libraries GNU / Diab Compilers 3. Software Compilation MDD MPD PAO BDD MPD PAO BDD Executable in on-chip memory boot.o (for PPC) xmdstub.elf (for MB) *.a, *.h, Executable Drivers for Processor IP or MYIP Executable in off-chip memory ? GDB / XMD Download to Board “Xilinx Confidential”

18. XPS Manages Source Code and Setup Compiler Options Supports GNU and Diab Compilers SW Development Flow 1. Specify Software Architecture MHS SW Configuration 2. Automatic Software BSP/Library Generation LibGen GNU/ Diab Compilers 3. Software Compilation Executable in on-chip memory Executable Executable in off-chip memory ? GDB / XMD Download to Board “Xilinx Confidential”

19. Embedded Development Flow • Embedded System Design Consists of • Hardware design • Software design • HW / SW co-verification (Simulation & debug ) XPS Hardware Design Simulation HW-SW Partitioning HW-SW Co-Verification Debug Software Design “Xilinx Confidential”

20. Simulation Flow • MVS • Microprocessor Verification Specification • SimGen • Simulation Model Generator • Generates and configures simulation models for a specified hardware. Simulation Flow 1. Specify Simulation Platform Sim Configuration MVS 2. Automatic Simulation Platform Generation SimGen • MVS Example • PARAMETER HW_SPEC_FILE = system.mhs • PARAMETER SW_SPEC_FILE = system.mss • PARAMETER LANGUAGE = VHDL • PARAMETER SIMULATOR = mti • PARAMETER SIM_MODEL = BEHAVIORAL • .. Modelsim / Verilog XL 3. Simulator “Xilinx Confidential”

21. Simulation Flow • SimGen • Generates and configures simulation models, do-files • Used in conjunction with PlatGen and MHS • Takes ELF + BMM to generate models to initialize BRAMs MHS File Hardware Flow Software Flow MVS File HDL Wrapper(s) NGC Executable SimGen BMM Processor IP Sim Model(s) DO File Compile list Map libraries *_Init.vhd (Init BRAM), HDL Wrappers Simulator PowerPC SWIFT Model “Xilinx Confidential”

22. Simulation Model Generator(SimGen) • Simulation Models Supported by SimGen • Behavioral (functional simulation) • Processor IP (including MicroBlaze) simulation models are provided • Structural (gate-level simulation) • Structural with timing • Simulators Supported by SimGen • ModelSim • Verilog-XL • Languages Supported by SimGen • VHDL • Verilog (gate-level) “Xilinx Confidential”

23. Bus Function Model Generator(BfmGen) • Creates Testbench for Module Level Verification • Generates PLB / OPB / DCR transactions (Test Stimulus) • Used in Conjunction with IBM CoreConnect Toolkit • Need CoreConnect license from IBM • Need to install CoreConnect toolkit BFM Does my design work ? My Peripheral * For bus monitors, also take a look at the solution from Chipscope Integrated Bus Analyzer (IBA) “Xilinx Confidential”

24. Embedded Development Flow • Embedded System Design Consists of • Hardware design • Software design • HW / SW co-verification (Simulation & Debug) XPS Hardware Design Simulation HW-SW Partitioning HW-SW Co-Verification Software Design Debug “Xilinx Confidential”

25. Debug Using XMD • Plumbing and synchronization between host-side application and: • Other host-side applications • Actual (hardware) targets • Tcl interface Debug with actual hardware of PowerPC • XMD for PowerPC • GDB connects to XMD connects to Parallel IV cable XMD GDB Remote (TCP/IP) LAB1 PPC “Xilinx Confidential”

26. Debug Using XMD • XMD for MicroBlaze • Connects to: • ISS for cycle accurate SW debug • UART, or JTAG_UART for HW target debug Cycle Accurate ISS for MB Debug with actual hardware of MB XMD GDB Remote (TCP/IP) XMD Protocol GDB Remote XMD LAB1 (TCP/IP) “Xilinx Confidential”

27. Design for Debug • PowerPC • Dedicate debug port in the hard macro (BDM) • BDM can shared with FPGA’s JTAG Pins • But there is a rule in FPGA: ALL or NONE !!! *XMD currently supports 2VP4 / P7 only LAB1 jtagppc_cntlr.vhd : U0_JTAGPPC : JTAGPPC Port Map ( TCK => JTGC405TCK, --o TDIPPC => JTGC405TDI, --o TMS => JTGC405TMS, --o TDOPPC => C405JTGTDO, --i TDOTSPPC => C405JTGTDOEN --i PPC PPC PPC PPC *Find out more information regarding to Wind River’s requirement! “Xilinx Confidential”

28. Design for Debug (cont.) • MicroBlaze • No dedicate debug interface (future plan) • Use UART(Serial Cable) or JTAG(Parallel Cable) to connect • Small debug program “XMDStub” resides in the memory LAB1 JTAG UART UART Lite OPB OR OPB MicroBlaze MicroBlaze MicroBlaze MicroBlaze “Xilinx Confidential”

29. Conclusion: Xilinx Platform Studio Architecture XPS provides project management interfaces XPS coordinates multiple point tools with well defined interfaces XPS GUI provide user intuitive design entries Makefile flow engine is even more flexible to manage customed design methodologies in batch mode XPS Hardware Design Simulation HW-SW Partitioning HW-SW Co-Verification Debug Software Design “Xilinx Confidential”

30. Reference and Resources • Always: • Datasheets / Reference Guide • Forums / Tech Tips / Solutions • C to Bit tutorials - coming soon • EDK How-To Guide - coming soon • www.embedded.com “Xilinx Confidential”