POWERPC ARCHITECTURE. Term Paper Presentation by Umut Yazkurt CMPE 511 Fall 2003-2004. History. PowerPC is a RISC architecture . It was jointly designed by Apple, IBM, and Motorola by early 1990s .
Term Paper Presentation
Apple, IBM, and Motorola designed the first four members of the PowerPC microprocessor family simultaneously.
Architecture defines five types of registers :
Five important user mode SPRs are:
General Purpose Registers :
Floating Point Registers :
Device Control Registers :
Machine State Register :
* Unsigned byte
* Unsigned halfword
* Signed halfword
* Unsigned word
* Signed word
* Unsigned doubleword
* Byte Strings: From 0 – 128 bytes in length
ALU, Floating Point , Load/Store, Branch, Condition and Synchronization Instructions
Three types of operand addressing :
* Base address in a GPR + a 16-bit sign-extended literal
* Base address in a GPR + displacement from another GPR
Nine Execution Units
G4e’s microarchitecture with emphasis on pipeline stages of the front end and the functional units.