Dmt 121 electronic devices
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DMT 121 – ELECTRONIC DEVICES - PowerPoint PPT Presentation

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DMT 121 – ELECTRONIC DEVICES. CHAPTER 5: FIELD-EFFECT TRANSISTOR (FET). TYPES OF FET. Junction Field-Effect Transistor (JFET) N-channel P-channel Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) Enhancement-MOSFET Depletion-MOSFET. FET vs BJT. THE JFET.

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Dmt 121 electronic devices




Types of fet

  • Junction Field-Effect Transistor (JFET)

  • N-channel

  • P-channel

  • Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)

  • Enhancement-MOSFET

  • Depletion-MOSFET

The jfet

  • BJT – current controlled, IC is direct function of IB

  • FET– voltage controlled, ID is a direct function of the voltage VGS applied to the input circuit.

FIGURE: (a) Current-controlled and (b) voltage-controlled amplifiers.


  • 3 terminal:

  • Drain – upper end

  • Source – lower end

  • Gate – 2 p/n-type regions are diffuse in the n/p-type material to form a channel.

FIGURE: A representation of the basic structure of the two types of JFET.

Jfet structures symbols
JFET Structures & Symbols

JFET Structures

JFET Symbols

Basic operation of jfet
Basic Operation of JFET

  • VDD provides a drain-to-source voltage and supplies current from drain to source.

  • VGG sets the reverse-bias voltage between gate and source.

  • JFET is always operated with the gate-source pn junction reverse-biased.

  • Reverse-biased of gate-source junction with negative gate voltage produce a depletion region along pn junction – increase resistance by restricting the channel width

Basic operation of jfet1
Basic Operation of JFET

Figure: Greater VGG narrows the channel (between the white areas) which increases the resistance of the channel and decreases ID.

Figure: Less VGG widens the channel (between the white areas) which decreases the resistance of the channel and increases ID.

Basic operation of jfet2
Basic Operation of JFET

  • The channel width and the channel resistance can be controlled by varying the gate voltage – controlling the amount of drain current, ID.

  • The depletion region (white area) created by reverse bias.

  • Wider toward the drain-end of the channel – reverse-bias voltage between gate and drain is greater than voltage between gate and source.

Jfet analogy
JFET Analogy

JFET operation can be compared to a water spigot.

  • The source of water pressure is the accumulation of electrons at the negative pole of the drain-source voltage.

  • The drain of water is the electron deficiency (or holes) at the positive pole of the applied voltage.

  • The control of flow of water is the gate voltage that controls the width of the n-channel and, therefore, the flow of charges from source to drain.

Jfet characteristic
JFET Characteristic

Figure: JFET with VGS=0 V and variable VDS (VDD)

Figure: Drain Characteristic

Jfet characteristics and parameters v gs 0
JFET Characteristics and Parameters, VGS = 0

  • VGS = 0 V by shorting the gate to source (both grounded).

  • ID increases proportionally with increases of VDD (VDS increases as VDDis increased). This is called the ohmic region (point A to B).

  • In this area (ohmic region) the channel resistance is essentially constant because of the depletion region is not large enough to have sufficient effect  VDS and ID are related by Ohm’s law

  • In JFET, IG = 0  an important characteristic for JFET

Jfet characteristics and parameters v gs 01
JFET Characteristics and Parameters, VGS = 0

  • At point B, the curve levels off and enter the active region where ID constant.

  • Value of VDS at which ID becomes constant is pinch-off voltage, VP.

  • As VDD increase from point B to point C, the reverse-bias voltage from gate to drain (VGD) produces a depletion region large enough to offset the increase in VDS, thus keeping ID relatively constant.

  • VDS increase above VP, produce almost constant ID called IDSS.

  • IDSS(drain to source current with gate shorted) is max drain current at VGS = 0V

Jfet characteristics and parameters v gs 02
JFET Characteristics and Parameters, VGS = 0

  • Breakdown occurs at point C when ID begins to increase very rapidly with any further increase in VDS.

  • It can result irreversible damage to the device

  • So JFETs are always operated below breakdown and within the constant-current area (between points B and C on the graph)

V gs controls i d
VGS controls ID

V gs controls i d1
VGS controls ID

  • As VGS is set to increasingly more negative by adjusting VGG. A family of drain characteristic curves is produced.

  • Notice that ID decrease as the magnitude of VGS is increased to larger negative value narrowing of channel.

  • For each increase in VGS, the JFET reaches pinch-off (constant current begins) at values of VDS less than VP.

  • The amount of drain current is controlled by VGS.

Cutoff voltage
Cutoff Voltage

  • Value of VGS that makes ID ≈ 0A is the cutoff voltage, VGS(off).

  • JFET must operated between VGS=0V and VGS(off).

  • In n-channel JFET: VGS has large –ve value, ID is reduce to zero.

  • Cutoff effect due to widening of depletion region.

V gs controls i d2
VGS controls ID

Pinch off cutoff voltage
Pinch-Off & Cutoff Voltage

  • Pinch-off voltage, VP = value of VDS at which drain current becomes constant and equal to IDSS at VGS = 0V

  • Pinch-off occurs for VDS value less than VP when VGS is nonzero.

  • VGS(off) & VP are equal in magnitude but opposite sign

  • VGS(off) = -VP

P channel jfet operation
P-channel JFET operation

  • Same as n-channel JFET except required negative VDD and positive VGS.


VGS(off)= -4V and IDSS= 12mA. Determine the minimum value of VDD required to put the device in constant-current region of operation when VGS= 0V.

Jfet transfer characteristic1
JFET Transfer Characteristic

  • The transfer characteristic of input-to-output is not as straightforward in a JFET as it is in a BJT.

  • In a BJT,  indicates the relationship between IB (input) and IC (output).

  • IC = IB

  • In a JFET, the relationship of VGS (input) and ID (output) is a little more complicated:

Control Variable


Control Variable


JFET Transfer Curve

This graph shows the value of ID for a given value of VGS.

When VGS = 0; ID = IDSS

When VGS = VGS (off) = VP; ID = 0 mA

Plotting jfet transfer curve

Step 1

Solving for VGS = 0V ID = IDSS

Step 2

Solving for VGS = Vp (VGS(off)) ID = 0A

Step 3

Solving for VGS = 0V to Vp

Plotting JFET Transfer Curve


JFET with IDSS = 9 mA and VGS(off) = -8V (max). Determine ID for VGS = 0V, -1V and -4V.


VGS = 0V, ID = 9mA

VGS = -1V, ID = 6.89mA

VGS = -4V, ID = 2.25mA

Jfet biasing
JFET Biasing

Just as we learned that the bipolar junction transistor must be biased for proper operation, the JFET too must be biased for operation. Let’s look at some of the methods for biasing JFETs. In most cases the ideal Q-point will be the middle of the transfer characteristic curve which is about half of the IDSS.

Jfet biasing1
JFET Biasing

  • JFET must be operated that gate-source junction is always reverse-biased.

  • VG=0V

Self bias

  • Since VG = 0V, IG = 0A

  • IS = ID

  • VS = IDRS

  • VGS = VG – VS = 0 – IDRS = -IDRS

  • VD = VDD – IDRD

  • VDS = VD – VS = VDD – ID(RD + RS)

Jfet biasing fixed bias configuration
JFET Biasing, Fixed- Bias Configuration

IG = 0 so VRG = IGRG = (0 A)RG = 0 then RG can be removed from the circuit.

RG only need in ac analysis through the input Vi

- VGG – VGS = 0


Jfet biasing fixed bias configuration1
JFET Biasing, Fixed- Bias Configuration

Drain-to-source voltage can be determined by applying Kirchoff’s voltage law



Source voltage to ground; VS = 0

Drain-to-source voltage can also be determined through;

VDS = VD – VS but VS = 0 then


Fig. 7.5 Measuring the quiescent values of ID and VGS.

Gate-to-source voltage

VGS = VG – VS ; since VS = 0


Since the configuration requires two dc supply, its use is limited and not included in the list of common FET configurations.

Jfet biasing self bias configuration
JFET Biasing, Self- Bias Configuration

Most common type of JFET bias. Eliminates the need for two dc supplies.

The controlling gate-to-source is determined by the voltage across a resistor RS.

For analysis, resistor RG replaced by a short circuit equivalent since IG = 0 A.

Jfet biasing self bias configuration1
JFET Biasing, Self- Bias Configuration

Voltage drop across source resistor, RS

VRS = ISRS; since IS = ID then


For indicated closed loop in the Figure 7.9

-VGS – VRS = 0



Drain current, ID:

Fig. 7.9 DC analysis of the self-bias configuration.

Jfet biasing self bias configuration2
JFET Biasing, Self- Bias Configuration

Voltage between drain-to-source, VDS


Since IS = ID






Voltage between gate-to-source, VGS

VGS = VG – VS;

Since VG = 0

VGS = -VS and VS = ISRS

Then VGS = - ISRS

Fig. 7.9 DC analysis of the self-bias configuration.

JFET Biasing, Self- Bias Configuration

The value of RSneeded to establish the computed VGS can be determined by the previously discussed relationship below.


The value of RDneeded can be determined by taking half of VDD and dividing it by ID.

RD = (VDD/2)/ID

JFET Biasing, Self- Bias Configuration

Remember the purpose of biasing is to set a point of operation (Q-point). In a self-biasing type JFET circuit the Q-point is determined by the given parameters of the JFET itself and values of RSand RD. Setting it at midpoint on the drain curve is most common.

One thing not mentioned in the discussion was RG. It’s value is arbitrary but it should be large enough to keep the input resistance high.

Jfet biasing voltage divider configuration
JFET Biasing, Voltage-Divider Configuration

The basic construction exactly the same with BJT, but the dc analysis quite different with IG = 0 for FET

The voltage at source, VS must be more positive than the voltage at the gate, VG in order to keep gate-source junction reverse-biased.

Jfet biasing voltage divider configuration1
JFET Biasing, Voltage-Divider Configuration

Gate-to-source analysis


Gate-to-source voltage; VGS = VG – VS

And source voltage is VS = VG – VGS

The drain current can be expressed as

Jfet biasing voltage divider configuration2
JFET Biasing, Voltage-Divider Configuration

Drain-to-source analysis