Verification Methodology of Gigabit Switch System

1. Verification Methodology of Gigabit Switch System 1999/9/9 Yi Ju Hwan

2. Agenda • Design flow & Verification • Example • Algorithm-level design & verification • RT-level design & verification • Gate-level verification • Introduction to Gigabit project • Verification methodology of gigabit switch system • Summary

3. Spec. Decision Spec. Design Flow Create Project

4. Design & Coding Simulation Design Verification Spec. Tape-out Design Flow

5. Fabrication Testing CHIP!!! Design Flow

6. Motion picture Broadcast system MPEG encoding MPEG bit stream Design & Verification Example

7. Motion picture file MPEG encoding Algorithm level Model MPEG player MPEG file Algorithm-level Design & Verification

8. Broadcast system interface model MPEG encoder model Camera interface Model MPEG player Motion picture file MPEG file RT-level Design & Verification

9. Motion picture Broadcast system Emulator MPEG bit stream Gate-level Verification (Hardware Emulation)

10. PC PC PC PC NP GMII PC SF GMII GMII PC GMII GMII PC GMII GMII PC GMII Gigabit Ethernet Switch Project • 8x8 Switch Fabric • 16 Gbps bandwidth • Gigabit Port Controller • Individual lookup engine • Full gigabit line-rate support

11. Expansion • 32x32 Switch with 12 SF, 32 PC NP PC PC PC PC PC PC PC PC PC PC PC PC PC PC PC PC NP SF SF SF SF SF SF SF SF SF SF SF SF NP PC PC PC PC PC PC PC PC PC PC PC PC PC PC PC PC NP

12. Verification Strategy • Architecture-level verification • High-level description in C-language • Decision making about expansion scheme, architecture • Simulation with network environment model • RT-level description in Verilog HDL • Actual design & debugging with Virtual Network • Software emulation • PC with Verilog simulator • Verification with real network environment • Hardware emulation • Hardware prototype board with FPGA • Verification with other chipset (network processor, MAC interface)

13. Building Environment Model(Virtual Network) • Captured packets • Real application program • Controlled traffic • Use traffic generation routine of network simulator • Various packets • TCP, UDP, ARP, IPX... Virtual Network Environment Real Network Environment Packet capture Analysis & Filtering

14. GESIM(Architecture-level Verification) Simulator Scheduler Event Queue Executor Event Handler Parameters Vnet Vnet I/F Tx Model Debugger Unit Packets to be sent PC SF Received packets Vnet I/F Rx PC

15. Virtual Network with PLI(RT-level Design & Verification) C routine Verilog Simulator Parameters Vnet Vnet I/F Tx MAC interface (PLI) Packets to be sent PC SF Received packets Vnet I/F Rx MAC interface (PLI) PC

16. Software Emulation Real Network Environment Network Processor(PLI) PC Verilog Simulator MAC (NIC) MAC interface (PLI) PC SF SSRAM SDRAM MAC (NIC) MAC interface (PLI) PC SSRAM SDRAM

17. Advantage & Disadvantage of Software Emulation • No design change • Easy to debug • Easy to build system • No hardware design overhead • Functionality check with real network system • No hardware interface verification • Slow emulation speed • 300k gate RTL simulation: 100 cycle/sec @ 143MHz Ultra Sparc with VCS

18. Hardware Emulation Real Network Environment Prototype board Network Processor MAC (LUC3M08) PHY PC (FPGA) SF (FPGA) SSRAM SDRAM MAC (LUC3M08) PHY PC (FPGA) SSRAM SDRAM

19. Summary • Spec. decision • Architecture level-simulation & verification • Design • System modeling • RT-level simulation & verification • Emulation • Prototype board, Emulator, FPGA