Verification Methodology for sub-micron Technologies

1. ATLAS - CMS 65nm pixel ASIC meeting 26thNovember 2012 Verification Methodology for sub-micron Technologies T. Hemperek

2. Moore's law in HEP

3. Switch to big “D”, little “A”

4. FE-I4

5. Design Flow

6. RTL Verification • Verification plan • Simulation • Equivalence checking • Assertion based verification • Formal verification • Metric Driven Verification

7. Verification Plan

8. Simulation – Verification Methodology Digital Mixed Signal

9. Equivalence checking • Equivalence checking • Formal equivalence checking also transistor level

10. Assertions based verification A pattern describes a proven solution to a recurring design problem // A start can only occur after a grant for an active requestassert property (@(posedgeclk) disable iff (~rst_n)req[*1:8] ##0 grant ##1 req |-> start);

11. Formal analysis // SystemVerilogAssertion propertyp_arb; @(posedgeclk) req|=> ##[0:2] gnt; endproperty assertproperty (p_arb);

12. Static verification checking and simulation

13. Metric Driven Verification

14. Implementation • Multi corner analysis • Variation aware STA • Signal integrity • Power/Rail analysis • Design for Yield • Design for manufacturing

15. Interconnect capacitances At the 90-nm generation and below, process variations are considered in extracting the 3D capacitance.

16. Multi Corner Multi Mode Analysis • Operation Modes • Sleep (10 kHz) • Active (100 MHz) • PVTCorener • +100C, 1.2V • -40C, 1V • Interconnect corners • MaxR • MaxC • MinR • MinC • MaxRC also for Analog

17. On chip variation Analysis On-chip variation analysis is one of the static timing analysis techniques for considering delay variations. Monte Carlo for Analog .

18. Signal integrity analysis With coupling capacitance dominating total capacitance (for some nets, coupling accounts for more than 80 percent of total capacitance), and with higher clock frequencies and lower supply voltages, nanometer designs suffer from an increased sensitivity to signal integrity (SI) effects such as crosstalk-induced delay changes and functional failures caused by crosstalk glitches.

19. Power and power rail verification

20. Rail verification Also for Analog and Mixed Signal Designs For full chip sign-off

21. Design for Yield Traditionally, single cut vias were used for routing random logic regions. Double cut vias can now be applied to improve manufacturing yield.

22. Design for Manufacturing

23. Questions?