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CS 252 Graduate Computer Architecture Lecture 2 - Metrics and Pipelining

CS 252 Graduate Computer Architecture Lecture 2 - Metrics and Pipelining. Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste http://inst.eecs.berkeley.edu/~cs252. Review from Last Time.

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CS 252 Graduate Computer Architecture Lecture 2 - Metrics and Pipelining

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  1. CS 252 Graduate Computer Architecture Lecture 2 - Metrics and Pipelining Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste http://inst.eecs.berkeley.edu/~cs252

  2. Review from Last Time • Computer Architecture >> instruction sets • Computer Architecture skill sets are different • 5 Quantitative principles of design • Quantitative approach to design • Solid interfaces that really work • Technology tracking and anticipation • CS 252 to learn new skills, transition to research • Computer Science at the crossroads from sequential to parallel computing • Salvation requires innovation in many fields, including computer architecture • Opportunity for interesting and timely CS 252 projects exploring CS at the crossroads • RAMP as experimental platform CS252-Fall’07

  3. Review (continued) • Other fields often borrow ideas from architecture • Quantitative Principles of Design • Take Advantage of Parallelism • Principle of Locality • Focus on the Common Case • Amdahl’s Law • The Processor Performance Equation • Careful, quantitative comparisons • Define, quantity, and summarize relative performance • Define and quantity relative cost • Define and quantity dependability • Define and quantity power • Culture of anticipating and exploiting advances in technology • Culture of well-defined interfaces that are carefully implemented and thoroughly checked CS252-Fall’07

  4. Metrics used to Compare Designs • Cost • Die cost and system cost • Execution Time • average and worst-case • Latency vs. Throughput • Energy and Power • Also peak power and peak switching current • Reliability • Resiliency to electrical noise, part failure • Robustness to bad software, operator error • Maintainability • System administration costs • Compatibility • Software costs dominate CS252-Fall’07

  5. Cost of Processor • Design cost (Non-recurring Engineering Costs, NRE) • dominated by engineer-years (~$200K per engineer year) • also mask costs (exceeding $1M per spin) • Cost of die • die area • die yield (maturity of manufacturing process, redundancy features) • cost/size of wafers • die cost ~= f(die area^4) with no redundancy • Cost of packaging • number of pins (signal + power/ground pins) • power dissipation • Cost of testing • built-in test features? • logical complexity of design • choice of circuits (minimum clock rates, leakage currents, I/O drivers) Architect affects all of these CS252-Fall’07

  6. System-Level Cost Impacts • Power supply and cooling • Support chipset • Off-chip SRAM/DRAM/ROM • Off-chip peripherals CS252-Fall’07

  7. What is Performance? • Latency (or response time or execution time) • time to complete one task • Bandwidth (or throughput) • tasks completed per unit time CS252-Fall’07

  8. performance(x) = 1 execution_time(x) Performance(X) Execution_time(Y) n = = Performance(Y) Execution_time(X) Definition: Performance • Performance is in units of things per sec • bigger is better • If we are primarily concerned with response time " X is n times faster than Y" means CS252-Fall’07

  9. Performance Guarantees Average Rate: A > B > C Worst-case Rate: A < B < C Inputs C B A Execution Rate CS252-Fall’07

  10. Types of Benchmark • Synthetic Benchmarks • Designed to have same mix of operations as real workloads, e.g., Dhrystone, Whetstone • Toy Programs • Small, easy to port. Output often known before program is run, e.g., Nqueens, Bubblesort, Towers of Hanoi • Kernels • Common subroutines in real programs, e.g., matrix multiply, FFT, sorting, Livermore Loops, Linpack • Simplified Applications • Extract main computational skeleton of real application to simplify porting, e.g., NAS parallel benchmarks, TPC • Real Applications • Things people actually use their computers for, e.g., car crash simulations, relational databases, Photoshop, Quake CS252-Fall’07

  11. Performance: What to measure • Usually rely on benchmarks vs. real workloads • To increase predictability, collections of benchmark applications-- benchmark suites -- are popular • SPECCPU: popular desktop benchmark suite • CPU only, split between integer and floating point programs • SPECint2000 has 12 integer, SPECfp2000 has 14 integer pgms • SPECCPU2006 to be announced Spring 2006 • SPECSFS (NFS file server) and SPECWeb (WebServer) added as server benchmarks • Transaction Processing Council measures server performance and cost-performance for databases • TPC-C Complex query for Online Transaction Processing • TPC-H models ad hoc decision support • TPC-W a transactional web benchmark • TPC-App application server and web services benchmark CS252-Fall’07

  12. System Rate (Task 1) Rate (Task 2) A 10 20 B 20 10 Summarizing Performance Which system is faster? CS252-Fall’07

  13. Average Average Average System System System Rate (Task 1) Rate (Task 1) Rate (Task 1) Rate (Task 2) Rate (Task 2) Rate (Task 2) 1.00 1.25 15 A A A 0.50 10 1.00 2.00 1.00 20 1.00 1.25 15 B B B 2.00 20 1.00 1.00 0.50 10 … depends who’s selling Average throughput Throughput relative to B Throughput relative to A CS252-Fall’07

  14. Summarizing Performance over Set of Benchmark Programs Arithmetic mean of execution times ti (in seconds) 1/niti Harmonic mean of execution rates ri (MIPS/MFLOPS) n/ [i(1/ri)] • Both equivalent to workload where each program is run the same number of times • Can add weighting factors to model other workload distributions CS252-Fall’07

  15. Normalized Execution Timeand Geometric Mean • Measure speedup up relative to reference machine ratio = tRef/tA • Average time ratios using geometric mean n(I ratioi ) • Insensitive to machine chosen as reference • Insensitive to run time of individual benchmarks • Used by SPEC89, SPEC92, SPEC95, …, SPEC2006 ….. But beware that choice of reference machine can suggest what is “normal” performance profile: CS252-Fall’07

  16. Vector/Superscalar Speedup • 100 MHz Cray J90 vector machine versus 300MHz Alpha 21164 • [LANL Computational Physics Codes, Wasserman, ICS’96] • Vector machine peaks on a few codes???? CS252-Fall’07

  17. Superscalar/Vector Speedup • 100 MHz Cray J90 vector machine versus 300MHz Alpha 21164 • [LANL Computational Physics Codes, Wasserman, ICS’96] • Scalar machine peaks on one code??? CS252-Fall’07

  18. How to Mislead with Performance Reports • Select pieces of workload that work well on your design, ignore others • Use unrealistic data set sizes for application (too big or too small) • Report throughput numbers for a latency benchmark • Report latency numbers for a throughput benchmark • Report performance on a kernel and claim it represents an entire application • Use 16-bit fixed-point arithmetic (because it’s fastest on your system) even though application requires 64-bit floating-point arithmetic • Use a less efficient algorithm on the competing machine • Report speedup for an inefficient algorithm (bubblesort) • Compare hand-optimized assembly code with unoptimized C code • Compare your design using next year’s technology against competitor’s year old design (1% performance improvement per week) • Ignore the relative cost of the systems being compared • Report averages and not individual results • Report speedup over unspecified base system, not absolute times • Report efficiency not absolute times • Report MFLOPS not absolute times (use inefficient algorithm) [ David Bailey “Twelve ways to fool the masses when giving performance results for parallel supercomputers” ] CS252-Fall’07

  19. Benchmarking for Future Machines • Variance in performance for parallel architectures is going to be much worse than for serial processors • SPECcpu means only really work across very similar machine configurations • What is a good benchmarking methodology? • Possible CS252 project • Berkeley View Techreport has “Dwarves” as major types of code that must run well (http://view.eecs.berkeley.edu) • Can you construct a parallel benchmark methodology from Dwarves? CS252-Fall’07

  20. Power and Energy • Energy to complete operation (Joules) • Corresponds approximately to battery life • (Battery energy capacity actually depends on rate of discharge) • Peak power dissipation (Watts = Joules/second) • Affects packaging (power and ground pins, thermal design) • di/dt, peak change in supply current (Amps/second) • Affects power supply noise (power and ground pins, decoupling capacitors) CS252-Fall’07

  21. Peak Power versus Lower Energy • System A has higher peak power, but lower total energy • System B has lower peak power, but higher total energy Peak A Peak B Power Integrate power curve to get energy Time CS252-Fall’07

  22. CS252 Administrivia Instructor: Prof. Krste Asanovic Office: 645 Soda Hall, krste@eecs Office Hours: M 1-3PM, 645 Soda Hall T. A.: Rose Liu, rfl@eecs Office Hours: W 4-5PM, 751 Soda Hall Lectures: Tu/Th, 9:30-11:00AM 203 McLaughlin Text: Computer Architecture: A Quantitative Approach, 4th Edition (Oct, 2006) Web page: http://inst.eecs.berkeley.edu/~cs252 Lectures available online <6:00 AM day of lecture CS252-Fall’07

  23. CS252 Updates • Prereq quiz will cover: • Finite state machines • ISA designs & MIPS assembly code programming (today’s lecture) • Simple pipelining (single-issue, in-order, today’s lecture) • Simple caches (Tuesday’s lecture) • Will try using Bspace this term to manage course private material (readings, assignments) • https://bspace.berkeley.edu/portal • Book order late at book store, will try and get you temporary copies of text CS252-Fall’07

  24. A "Typical" RISC ISA • 32-bit fixed format instruction (3 formats) • 32 32-bit GPR (R0 contains zero, DP take pair) • 3-address, reg-reg arithmetic instruction • Single address mode for load/store: base + displacement • no indirection • Simple branch conditions • Delayed branch see: SPARC, MIPS, HP PA-Risc, DEC Alpha, IBM PowerPC, CDC 6600, CDC 7600, Cray-1, Cray-2, Cray-3 CS252-Fall’07

  25. Example: MIPS (­ MIPS) Register-Register 6 5 11 10 31 26 25 21 20 16 15 0 Op Rs1 Rs2 Rd Opx Register-Immediate 31 26 25 21 20 16 15 0 immediate Op Rs1 Rd Branch 31 26 25 21 20 16 15 0 immediate Op Rs1 Rs2/Opx Jump / Call 31 26 25 0 target Op CS252-Fall’07

  26. signals Datapath vs Control Datapath Controller • Datapath: Storage, FU, interconnect sufficient to perform the desired functions • Inputs are Control Points • Outputs are signals • Controller: State machine to orchestrate operation on the data path • Based on desired function and signals Control Points CS252-Fall’07

  27. Approaching an ISA • Instruction Set Architecture • Defines set of operations, instruction format, hardware supported data types, named storage, addressing modes, sequencing • Meaning of each instruction is described by RTL on architected registers and memory • Given technology constraints assemble adequate datapath • Architected storage mapped to actual storage • Function units to do all the required operations • Possible additional storage (eg. MAR, MBR, …) • Interconnect to move information among regs and FUs • Map each instruction to sequence of RTLs • Collate sequences into symbolic controller state transition diagram (STD) • Lower symbolic STD to control points • Implement controller CS252-Fall’07

  28. Adder 4 Address Inst ALU 5 Steps of MIPS DatapathFigure A.2, Page A-8 Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc Memory Access Write Back Next PC MUX Next SEQ PC Zero? RS1 Reg File MUX RS2 Memory Data Memory L M D RD MUX MUX Sign Extend IR <= mem[PC]; PC <= PC + 4 Imm WB Data Reg[IRrd] <= Reg[IRrs] opIRop Reg[IRrt] CS252-Fall’07

  29. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU 5 Steps of MIPS DatapathFigure A.3, Page A-9 Instruction Fetch Execute Addr. Calc Memory Access Instr. Decode Reg. Fetch Write Back Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX IR <= mem[PC]; PC <= PC + 4 Sign Extend WB Data Imm A <= Reg[IRrs]; B <= Reg[IRrt] RD RD RD rslt <= A opIRop B WB <= rslt Reg[IRrd] <= WB CS252-Fall’07

  30. jmp br LD RI r <= A + IRim r <= A opIRop IRim if bop(A,b) PC <= PC+IRim PC <= IRjaddr WB <= r WB <= Mem[r] Reg[IRrd] <= WB Reg[IRrd] <= WB Inst. Set Processor Controller IR <= mem[PC]; PC <= PC + 4 Ifetch opFetch-DCD A <= Reg[IRrs]; B <= Reg[IRrt] JSR JR ST RR r <= A opIRop B WB <= r Reg[IRrd] <= WB CS252-Fall’07

  31. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU 5 Steps of MIPS DatapathFigure A.3, Page A-9 Instruction Fetch Execute Addr. Calc Memory Access Instr. Decode Reg. Fetch Write Back Next PC MUX Next SEQ PC Next SEQ PC Zero? RS1 Reg File MUX Memory RS2 Data Memory MUX MUX Sign Extend WB Data Imm RD RD RD • Data stationary control • local decode for each instruction phase / pipeline stage CS252-Fall’07

  32. Reg Reg Reg Reg Reg Reg Reg Reg Ifetch Ifetch Ifetch Ifetch DMem DMem DMem DMem ALU ALU ALU ALU Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Visualizing PipeliningFigure A.2, Page A-8 Time (clock cycles) I n s t r. O r d e r CS252-Fall’07

  33. Pipelining is not quite that easy! • Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle • Structural hazards: HW cannot support this combination of instructions (single person to fold and put clothes away) • Data hazards: Instruction depends on result of prior instruction still in the pipeline (missing sock) • Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps). CS252-Fall’07

  34. Reg Reg Reg Reg Reg Reg Reg Reg Reg Reg Ifetch Ifetch Ifetch Ifetch DMem DMem DMem DMem ALU ALU ALU ALU ALU One Memory Port/Structural HazardsFigure A.4, Page A-14 Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 I n s t r. O r d e r Load DMem Instr 1 Instr 2 Instr 3 Ifetch Instr 4 CS252-Fall’07

  35. Reg Reg Reg Reg Reg Reg Reg Reg Ifetch Ifetch Ifetch Ifetch DMem DMem DMem ALU ALU ALU ALU Bubble Bubble Bubble Bubble Bubble One Memory Port/Structural Hazards(Similar to Figure A.5, Page A-15) Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 I n s t r. O r d e r Load DMem Instr 1 Instr 2 Stall Instr 3 How do you “bubble” the pipe? CS252-Fall’07

  36. Speed Up Equation for Pipelining For simple RISC pipeline, CPI = 1: CS252-Fall’07

  37. Example: Dual-port vs. Single-port • Machine A: Dual ported memory (“Harvard Architecture”) • Machine B: Single ported memory, but its pipelined implementation has a 1.05 times faster clock rate • Ideal CPI = 1 for both • Loads are 40% of instructions executed SpeedUpA = Pipeline Depth/(1 + 0) x (clockunpipe/clockpipe) = Pipeline Depth SpeedUpB = Pipeline Depth/(1 + 0.4 x 1) x (clockunpipe/(clockunpipe / 1.05) = (Pipeline Depth/1.4) x 1.05 = 0.75 x Pipeline Depth SpeedUpA / SpeedUpB = Pipeline Depth/(0.75 x Pipeline Depth) = 1.33 • Machine A is 1.33 times faster CS252-Fall’07

  38. Reg Reg Reg Reg Reg Reg Reg Reg Reg Reg ALU ALU ALU ALU ALU Ifetch Ifetch Ifetch Ifetch Ifetch DMem DMem DMem DMem DMem EX WB MEM IF ID/RF I n s t r. O r d e r add r1,r2,r3 sub r4,r1,r3 and r6,r1,r7 or r8,r1,r9 xor r10,r1,r11 Data Hazard on R1Figure A.6, Page A-17 Time (clock cycles) CS252-Fall’07

  39. Three Generic Data Hazards • Read After Write (RAW)InstrJ tries to read operand before InstrI writes it • Caused by a “Dependence” (in compiler nomenclature). This hazard results from an actual need for communication. I: add r1,r2,r3 J: sub r4,r1,r3 CS252-Fall’07

  40. I: sub r4,r1,r3 J: add r1,r2,r3 K: mul r6,r1,r7 Three Generic Data Hazards • Write After Read (WAR)InstrJ writes operand before InstrI reads it • Called an “anti-dependence” by compiler writers.This results from reuse of the name “r1”. • Can’t happen in MIPS 5 stage pipeline because: • All instructions take 5 stages, and • Reads are always in stage 2, and • Writes are always in stage 5 CS252-Fall’07

  41. I: sub r1,r4,r3 J: add r1,r2,r3 K: mul r6,r1,r7 Three Generic Data Hazards • Write After Write (WAW)InstrJ writes operand before InstrI writes it. • Called an “output dependence” by compiler writersThis also results from the reuse of name “r1”. • Can’t happen in MIPS 5 stage pipeline because: • All instructions take 5 stages, and • Writes are always in stage 5 • Will see WAR and WAW in more complicated pipes CS252-Fall’07

  42. Reg Reg Reg Reg Reg Reg Reg Reg Reg Reg ALU ALU ALU ALU ALU Ifetch Ifetch Ifetch Ifetch Ifetch DMem DMem DMem DMem DMem I n s t r. O r d e r add r1,r2,r3 sub r4,r1,r3 and r6,r1,r7 or r8,r1,r9 xor r10,r1,r11 Forwarding to Avoid Data HazardFigure A.7, Page A-19 Time (clock cycles) CS252-Fall’07

  43. ALU HW Change for ForwardingFigure A.23, Page A-37 ID/EX EX/MEM MEM/WR NextPC mux Registers Data Memory mux mux Immediate What circuit detects and resolves this hazard? CS252-Fall’07

  44. Reg Reg Reg Reg Reg Reg Reg Reg Reg Reg ALU ALU ALU ALU ALU Ifetch Ifetch Ifetch Ifetch Ifetch DMem DMem DMem DMem DMem I n s t r. O r d e r add r1,r2,r3 lw r4, 0(r1) sw r4,12(r1) or r8,r6,r9 xor r10,r9,r11 Forwarding to Avoid LW-SW Data HazardFigure A.8, Page A-20 Time (clock cycles) CS252-Fall’07

  45. Reg Reg Reg Reg Reg Reg Reg Reg ALU ALU ALU ALU Ifetch Ifetch Ifetch Ifetch DMem DMem DMem DMem lwr1, 0(r2) I n s t r. O r d e r sub r4,r1,r6 and r6,r1,r7 or r8,r1,r9 Data Hazard Even with ForwardingFigure A.9, Page A-21 Time (clock cycles) CS252-Fall’07

  46. Reg Reg Reg ALU Ifetch Ifetch Ifetch Ifetch DMem Bubble ALU ALU Reg Reg DMem DMem Bubble Reg Reg Data Hazard Even with Forwarding(Similar to Figure A.10, Page A-21) Time (clock cycles) I n s t r. O r d e r lwr1, 0(r2) sub r4,r1,r6 and r6,r1,r7 Bubble ALU DMem or r8,r1,r9 How is this detected? CS252-Fall’07

  47. Software Scheduling to Avoid Load Hazards Fast code: LW Rb,b LW Rc,c LW Re,e ADD Ra,Rb,Rc LW Rf,f SW a,Ra SUB Rd,Re,Rf SW d,Rd Try producing fast code for a = b + c; d = e – f; assuming a, b, c, d ,e, and f in memory. Slow code: LW Rb,b LW Rc,c ADD Ra,Rb,Rc SW a,Ra LW Re,e LW Rf,f SUB Rd,Re,Rf SW d,Rd Compiler optimizes for performance. Hardware checks for safety. CS252-Fall’07

  48. Reg Reg Reg Reg Reg Reg Reg Reg Reg Reg ALU ALU ALU ALU ALU Ifetch Ifetch Ifetch Ifetch Ifetch DMem DMem DMem DMem DMem 10: beq r1,r3,36 14: and r2,r3,r5 18: or r6,r1,r7 22: add r8,r1,r9 36: xor r10,r1,r11 Control Hazard on BranchesThree Stage Stall What do you do with the 3 instructions in between? How do you do it? Where is the “commit”? CS252-Fall’07

  49. Branch Stall Impact • If CPI = 1, 30% branch, Stall 3 cycles => new CPI = 1.9! • Two part solution: • Determine branch taken or not sooner, AND • Compute taken branch address earlier • MIPS branch tests if register = 0 or  0 • MIPS Solution: • Move Zero test to ID/RF stage • Adder to calculate new PC in ID/RF stage • 1 clock cycle penalty for branch versus 3 CS252-Fall’07

  50. MEM/WB ID/EX EX/MEM IF/ID Adder 4 Address ALU Pipelined MIPS DatapathFigure A.24, page A-38 Instruction Fetch Execute Addr. Calc Memory Access Instr. Decode Reg. Fetch Write Back Next SEQ PC Next PC MUX Adder Zero? RS1 Reg File Memory RS2 Data Memory MUX MUX Sign Extend WB Data Imm RD RD RD • Interplay of instruction set design and cycle time. CS252-Fall’07

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