IP ’07 Panel: Is networking the solution for interconnect design closure?. Dr. Miloš Krstić. GALAXY project. GALAXY project (GALS InterfAce for CompleX Digital SYstem Integration) will be funded in the FP7 program of EU. Project goals.
Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.
Dr. Miloš Krstić
solve system integration issues,
implement a complex GALS system on 45nm CMOS process,
explore the low EMI and low-power properties,
and robustness to process variability problems.
Clock-skew problems avoided
Potentials for power saving (50% power in NoCs is spent to clock net)
The synchronous design of NoC nodes at their optimum clock frequency
Possibilities for variation-tolerant on-chip interconnection schemes
Lack of convincing analysis and exploration frameworks, crossbenchmarking with synchronous solutions,
proven robustness against nanoscale physics effects,
creating with a complete automated synthesis flow for GALS NoCs