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A. Macchiolo, for the MPP, HLL, LAL, LPNHE, Glasgow, Liverpool consortium

I nterconnection of FE-I4 modules with SLID technology and Inter Chip Vias developed at Fraunhofer EMFT . A. Macchiolo, for the MPP, HLL, LAL, LPNHE, Glasgow, Liverpool consortium . AIDA 3 rd Annual Meeting, Vienna, 26 March 2014. 3D integration with FE -I4 chips with EMFT.

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A. Macchiolo, for the MPP, HLL, LAL, LPNHE, Glasgow, Liverpool consortium

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  1. Interconnection of FE-I4 modules with SLID technology and Inter Chip Vias developed at Fraunhofer EMFT A. Macchiolo, for the MPP, HLL, LAL, LPNHE, Glasgow, Liverpool consortium AIDA 3rd Annual Meeting, Vienna, 26 March 2014

  2. 3D integration with FE-I4 chips with EMFT Demonstrator module for SLID and TSV technologies based on ATLAS FE-I4 chip: • n-in-p pixel sensors • SLID as possible alternative to bump-bonding • Inter Chip Vias (ICV)with Via Last approach on the wire bonding pads to test the possibility of transport signal and services to the chip backside ICV SLID interconnection

  3. TSV on FE-I3 at EMFT • Processing sequence for FE-I3: • Via-etching in Bosch-process, ICV cross-section of 3x10 mm2 • insulation with TEOS (low T) • filling of vias with Tungsten • attachment to handle-wafer on the top side and thinning to desired thickness of chip ~ 60 mm • redistribution layer on the backside • SLID-interconnection to sensor wafer. • ICV preparation from back side after wafer thinning to 60 mm

  4. Inter Chip Vias in FE-I3: problems encountered • After etching of the isolation oxide of each ICV, it was observed that the W filling was not present and the ICVs were void. • Only TiN-CVD layer visible, done before W deposition as an adhesion layer • No W, only 60 nm thick TiN-coverage as electrical contact between frontside and backside available  high resistance for TSV-pin • Proceed anyhow with the SLID interconnection to the sensors to investigate feasibility of handling ultra-thin chips

  5. ICVs on the FE-I4 chip Metal stack on the FE-I4 wire bonding pad M1 has to be contacted through the ICV from the backside • Difficult to apply the ICV process developed for the FE-I3 chip : in the FE-I4 chip a stack of different metal layers and filling structures for many metal layers are present all over the wire bonding pads • EMFT is setting up a process to etch ICVs from the back-side, still with a reduced cross-section. The most challenging process step is the etching of the SiO2 layer beneath M1 through the ICV

  6. ICVs on the FE-I4 chip - process Backside approach with TMAH-etched cavities und backside ICVs • Pro’s: • Using thinned ASIC wafer with backside cavities, no glue layer/handling substrate • Allows for temperatures up to 400°C (ASIC-Device defines max. allowed temperature) • Several process steps up to the ICV-formation are not critical • Con’s: • Backside lithography, especially spray resist, might be a problem • Opening the TSV bottom for contacting the ASIC Pad might be a real challenge

  7. FE-I4 chip wafer availability 4 FE-I4B wafers ordered by MPP within the common IBL-ATLAS R&D order • 2 or 3 reserved for ICV trials at EMFT • One already at EMFT for process trials

  8. Design of the TSV on the FE-I4 chip • FE-I4 pad with poly-silicon layer, including filling structure • ICV must be placed outside poly-silicon structures, in correspondence of M1 (shown in purple)

  9. Design of the TSV on the FE-I4 chip • FE-I4 pad with poly-silicon layer, including filling structure • ICV designed with a cross-section of 9x60 mm2

  10. n-in-p FE-I4 sensors at CiS – 6” wafers • 12 wafers on p-type FZ material, 270 mm thick • RD50 common project • First sensor production at CIS on 6” wafers, several process steps outsourced at MPI Halle. Single Chip Modules Quad Modules • Wafers delivered a few weeks ago: a fraction of them has sufficient quality to proceed to the sensor interconnection to the read-out chip • Plans to interconnect this production partially with SLID at EMFT and partially with solder bump-bonding at IZM

  11. FE-I4 SCM design on new CIS 6” wafers • FE-I4: 25 mm x 250 mm pitch • 450 mm inactive edge on two sides SLID interconnection needs chip to wafer approach • Space left on the wafer between two neighboring FE-I4 sensors to place the chip cantilever • These sensor wafers will be used tohave an initial SLID interconnection run to FE-I4 chips without ICV • SLID tested up to now only with FE-I3 modules

  12. FE-I4 modules with reduced inactive edges • Using pixel sensors with active edges is possible to achieve four-side butttable modules • Trench doped by four-quadrant implantation • Pixel-to-trench distance as low as 50 mm • Next production at ADVACAM with ATLAS, CLIC, OMEGAPix sensors: 50, 100, 150 mm thickness • Plan to use this production for SLID interconnection to FE-I4 chips with ICVs

  13. Summary and Outlooks • Process under development at EMFT for the ICVs on the FE-I4 chip, by etching from the back-side • Design of the ICV placement on the FE-I4 wire bonding pads completed • Sensor production on 6” wafers to test SLID interconnection to FE-I4 chips with and without ICV completed • First run of SLID interconnection planned to FE-I4 chips without ICV

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