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Base System Builder

Base System Builder. Reference web site http://warp.rice.edu/svn/WARP/Documentation/Tutorials/XPS_Intro/html/sections/Base_System_Builder_-_FPGA_Board_v2.html. Launch Xilinx Platform Studio. Select Base System Builder to create a new design. Enter a path for your project.

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Base System Builder

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  1. Base System Builder

  2. Reference web site http://warp.rice.edu/svn/WARP/Documentation/Tutorials/XPS_Intro/html/sections/Base_System_Builder_-_FPGA_Board_v2.html

  3. Launch Xilinx Platform Studio

  4. Select Base System Builder to create a new design

  5. Enter a path for your project • Two key requirements:-The project file must be named 'system.xmp'-The project file must be saved to a folder with no spaces in its path - "C:\Documents and Settings\user\" will not work!

  6. Choose the option for a new design.

  7. Select Board • Select WARP Kits (FPGA/Clock/Radio Boards) and FPGA v2.2 / Radio 1.4 / Clock 1.1.

  8. Select Processor • The Xilinx EDK supports two embedded processors. The PowerPC processor is a "hard" processor core, embedded in the fabric of the Virtex-4 FPGA on the WARP FPGA board

  9. Configure PowerPC Processor

  10. Configure IO Interface • Enabled:- warp_v4_userio_all- rs232_db9- clock_board_config- radio_bridge_slot_2- radio_controller_0 • Disabled:- rs232_usb (a second serial port that is converted to USB on the board using an FTDI chip)- sysace_compactflash- TriMode_MAC_GMII- DDR2_SDRAM_2GB- radio_bridge_slot_1- radio_bridge_slot_3- radio_bridge_slot_4- eeprom_controller- analog_bridge_slot_4- user_io_board_controller_slot1

  11. Configure IO Interface

  12. Software Setup

  13. System Created

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