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ECSE-6230 Semiconductor Devices and Models I Lecture 13

ECSE-6230 Semiconductor Devices and Models I Lecture 13. Prof. Shayla Sawyer Bldg. CII, Rooms 8225 Rensselaer Polytechnic Institute Troy, NY 12180-3590 Tel. (518)276-2164 Fax. (518)276-2990 e-mail: sawyes@rpi.edu. April 1, 2014. sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html . 1.

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ECSE-6230 Semiconductor Devices and Models I Lecture 13

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  1. ECSE-6230Semiconductor Devices and Models ILecture 13 Prof. Shayla Sawyer Bldg. CII, Rooms 8225 Rensselaer Polytechnic Institute Troy, NY 12180-3590 Tel. (518)276-2164 Fax. (518)276-2990 e-mail: sawyes@rpi.edu April 1, 2014 sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html 1

  2. Lecture Outline Quasi-static MOS Capacitance Capacitance vs. Gate Voltage Oxide Charges C vs. V G vs. 

  3. Quasi-Static MOS Capacitance Low frequency thermal equilibrium MOS capacitance-voltage characteristics Surface potential and surface state density obtained Non uniformities in MOS MOS response to a linear voltage ramp Paper on course website “MOS Quasi” sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

  4. Capacitance vs. Gate Voltage Observations: (1) Asymmetric C-V curve  semiconductor type VT (threshold voltage) can be determined at Cmin. (2) When i is known, insulator thickness can be estimated from Cmax using ti = i / Cmax. The oxide thickness can be checked independently from ellipsometry. (3) Semiconductor doping concentration (if uniformly doped) can be determined as follows: (a) Measure Cmin = CTOTAL when Cs is a minimum. Find sm such that dCs / ds = 0, then sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

  5. Capacitance vs. Gate Voltage evaluate Cs (sm ) from NA, tox and Cmin relationship. Summarizing, Cmax  Cox  tox from (2). Cmin  NA (b) Meausre VFB. At flatband, CD,FB = s / LD = [ q2 s NA / ( kT ) ]1/2 What is CD,FB / Cox ? When C / Cox = 0.95, determine VG (accumulation). 0.95 = ( Cs / Cox ) / ( 1 + ( Cs / Cox ))  Cs / Cox = 19 From Eq. (2), Cs  ( 21/2/2) CD,FB exp ( - qs / 2kT ) From Eq. (1), VG|0.95 = VFB + s - 21/2 ( kT/q ) (CD,FB/Cox) exp ( - qs / 2kT ) sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

  6. Capacitance vs. Gate Voltage VG|0.95 = VFB + s - 21/2 ( kT/q ) (CD,FB/Ci) exp ( - qs / 2kT ) = VFB + s - 2 ( Cs / Cox ) ( kT/q )  VFB - 1V (4) Once VFB is known, Qox can be calculated from VFB = ms - Qox / Cox sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

  7. Capacitance vs. Gate Voltage Thinner oxide, smaller VT and larger variation of capacitance Modulation of Ψs is more effective sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

  8. Capacitance vs. Gate Voltage Carrier Response There is an ac gate signal superimposed on the dc gate signal. Majority carrier response follows the dielectric relaxation time ~ 1 to 10 ps or a frequency > 1011 Hz. Typically, an ac frequency of 1MHz is used for C-V curve. So, the majority carriers can follow the ac signal but the minority carriers are much slower to respond and cannot follow ac frequency higher than 100kHz. At an ac frequency of 1MHz, Cs is determined only by the majority carriers. sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

  9. Interface State Traps Interface state traps can be either donor- or acceptor-like, or amphoteric. Qit [ C cm-2 ] or Dit [ cm-2 eV -1 ] Equivalent distribution with a neutral level E0 above which the states are acceptor type and below which of donor type. When EF is above (below) E0, net charge is –(+). sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

  10. Interface State Traps To calculate the trapped charge, the occupancy takes on the value of 0 and 1 above and below EF Interface trapped charge can be calculated by Interface trap density From the change of Qit in response to EF or surface potential Ψs EF above E0 EF below E0 sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

  11. Interface State Traps When a voltage is applied, the Fermi level moves up or down with respect to the interface trap levels Change of charge in the interface trap occurs Affects the MIS capacitance and ideal MIS curve Product CitRit =τit, Cp, and Gp (frequency dependence) sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

  12. Interface State Traps At low frequency the equivalent circuit, Rit=0 and CD is parallel to Cit At high frequency Cit-Rit branch is ignored or open sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

  13. Qit Effect on C-V Stretching out in voltage direction. Extra charge has to fill the traps so it take more total charge or applied voltage to accomplish the same surface potential (band bending) Gap in capacitance between low frequency and high frequency curves, before Vmin near strong inversion α to Dit sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

  14. Interface State Traps Near midgap, Dit is relatively constant but increases toward the band edges Orientation is important In (100) Dit is an order of magnitude smaller than that in (111) Results are correlated with the number of available bonds per unit area (100) lower oxidation rate sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

  15. Fixed Oxide Charges Charge sheet very close to Si/SiO2 interface Generally positive Notice charge effect at the surface sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

  16. Qf Effect on C-V Vf = Qf / Cox sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

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