1 / 7

Chapter 2 (cont.)

EE314 Microprocessor Systems. Chapter 2 (cont.). Objectives: The different addressing modes and instruction types available The usefulness of interrupts Some of the differences between the 8086 and the 80286, 80386, 80486 and Pentium microprocessors.

borna
Download Presentation

Chapter 2 (cont.)

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. EE314Microprocessor Systems Chapter 2 (cont.) Objectives: The different addressing modes and instruction types available The usefulness of interrupts Some of the differences between the 8086 and the 80286, 80386, 80486 and Pentium microprocessors An Introduction to the 80x86 Microprocessor Family Based on "An Introduction to the Intel Family of Microprocessors" by James L. Antonakos

  2. 2.7 Addressing modes FFFFF FFFF0 FFFFF 00000 Reset instruction area F0000 E0000 D0000 C0000 B0000 A0000 90000 80000 70000 60000 50000 40000 30000 20000 10000 00000 A segment is a 64KB memory block, beginning at a multiple-of-16 (10H) address Real-Mode Addressing space Superposed segments • The addressing space of the processor in the real mode: • 20 address bits used • 1Mbyte wide • address 00000 to FFFFF • Logically Byte organized Overlapping segments The segment 38130H-4812FH The content of the used segment register is 3813H. A particular way to split memory in segments: non-overlapping 003FF 00000 Interrupt pointer table

  3. 2.7 Addressing modes Specify the operand to be used. To generate an address, a segment register is used also. Immediateaddressing: the operand is a number included in the instruction body. Registeraddressing: the operand is a register. MOV CX,1024 ADD AL , BL Directaddressing: the operand addressis a number in [] orthe value of a symbol (no [].) MOV AX,[3000] MOV BL,COUNTER Register indirectaddressing: the register enclosed in [ ] specifies the operand address. Indexedaddressing: the operand address is the sum of the value of the indexregister and a number, both enclosed in [ ]. MOV BX,[SI] The displacement is a signed 2’s complement byte or word MOV CL,[ BP - 4] MOV BX,[ SI + 10] Basedaddressing: is similar to indexed, but usingBP (base pointer) register. Based-indexedaddressing: the operand address is the sum of the values of BP and one of the indexregisters (SI or DI). MOV DS:[ BP + DI],AX Segment overriding Based-indexed with displacementaddressing: ads to the former an offset value. MOV DL,[ BP][ DI + 2] or MOV DL,[ BP + DI + 2] Portaddressing: used by input/output instructions. The address of the source port for IN or destinationport for OUT is a number or a register content. IN AL, DX OUT 80H , AL

  4. 2.7 Addressing modes Segment register CS DS ES FS GS SS Base register EAX EBX ECX EDX EBP ESI EDI ESP + Index register EAX EBX ECX EDX EBP ESI EDI + * Scale factor 1 2 4 8 none 8-bit 32-bit Displacement + Effective address 32-Bit Addressing Mode Ex: MOV EAX,[EBX][ECX*4+6] 0010 B4 09 MOV AH, 9 0012 8D 16 0000 R LEA DX, TABLE 0016 CD 21 INT 21H 0018 B4 09 MOV AH, 9 001A 66 8D 1E 0000 R LEA EBX, TABLE 001F 66 BA 00000002 MOV EDX, 2 0025 67 8D 14 93 LEA DX, [EBX][EDX*4] 0029 CD 21 INT 21H Prefixes to allow using 32-bit registers in real mode

  5. 2.8 Interrupts Hardware and Software Interrupts The nonmaskable interrupt is generated by en external device, via the NMI pin. Cannot be ignored by the microprocessor. • an external device, via the INTR pin (theexternal device has to specify the interrupt number). The maskable interrupts (0…FFH) can be generated by: Hardware interrupts (IF (interrupt flag) in FLAGS register enables or disables the P to accept maskable interrupts.) • microprocessor itself (i.e. when trying to divide by 0), (the interrupt number is hardware defined). Software interrupts using the INT instruction (followed by the interrupt number). The Interrupt Vector Table (or Interrupt Pointer Table) The memory block from address 00000 to 003FF. There are 1024 bytes, each of the 256 maskable interrupts uses four bytes to store the address where the corresponding ISR (Interrupt Service Routine) begins. The ISR address for interrupt number xx is stored beginning at address xx*4, in form CS:IP. From low to high address, the bytes are stored in the order: IP low, IP high, CS low and CS high (byte swapping). Example: The pointer for INT 21 is located at address: 21H*4=84H. C> debug -d 0:80 L 10 0000:0080 94 10 16 01 B4 16 26 07-4f 03 FB 0A 8A 03 FB 0A -q CS=0726H IP=16B4H INT 21 ISR: 08914H

  6. 2.9 The 8086: the first 80x86 Machine GND A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 40 8088 20 21 GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 40 8086 20 21 Vcc A15 A16/S3 A17/S4 A18/S5 A19/S6 ___ SS0 (HIGH) ___ MN/MX ___ RD ___ ____ HOLD (RQ/GT0) ___ ____ HLDA (RQ/GT1) ___ ______ WR (LOCK) __ __ IO/M (S2) __ __ DT/R (SI) ____ __ DEN (S0) ALE (QS0) _____ INTA (QS1) _____ TEST READY RESET Vcc AD15 A16/S3 A17/S4 A18/S5 A19/S6 ____ BHE/S7 ___ MN/MX ___ RD ___ ____ HOLD (RQ/GT0) ___ ____ HLDA (RQ/GT1) ___ ______ WR (LOCK) __ __ IO/M (S2) __ __ DT/R (SI) ____ __ DEN (S0) ALE (QS0) _____ INTA (QS1) _____ TEST READY RESET 8088 and 8086 pin assignments

  7. 2.9 The 8086: the first 80x86 Machine

More Related