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Xilinx On-Chip Debug

Chipscope 2. Debug and Verification is Critical. Debug and verification can account for over 40% of an FPGA design timeSerial nature of debug and verification can make it difficult to optimizeInefficient strategy may result in product launch delay Loss in market shareLoss of first-to-market adv

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Xilinx On-Chip Debug

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    1. This material exempt per Department of Commerce license exception TSU Xilinx On-Chip Debug

    2. Chipscope 2 Debug and Verification is Critical Debug and verification can account for over 40% of an FPGA design time Serial nature of debug and verification can make it difficult to optimize Inefficient strategy may result in product launch delay Loss in market share Loss of first-to-market advantages

    3. Chipscope 3

    4. Chipscope 4 Built For Debug - the Platform FPGA

    5. Chipscope 5 FPGA developers routinely identify logic analyzers as one of their top 2 in-circuit debug tools (the other top tool is usually a scope). FPGA customers determine early in their development process how many pins they want to dedicate to logic analysis. These customers often build in a test MUX that allows a customer to select a single group of signals to bring out to the pins at a single time. This technique minimizes the number of pins dedicated for debug. Typcial pin count for debug is in the range of 8 to 32 pins while internal nodes feeding the MUX is typically in the order of 32 to a hundred channels. When the customer finishes debug, the text MUX circuitry and pins for debug remain in the design. Taking them out would change the design characteristics and require a new round of debug. FPGA developers routinely identify logic analyzers as one of their top 2 in-circuit debug tools (the other top tool is usually a scope). FPGA customers determine early in their development process how many pins they want to dedicate to logic analysis. These customers often build in a test MUX that allows a customer to select a single group of signals to bring out to the pins at a single time. This technique minimizes the number of pins dedicated for debug. Typcial pin count for debug is in the range of 8 to 32 pins while internal nodes feeding the MUX is typically in the order of 32 to a hundred channels. When the customer finishes debug, the text MUX circuitry and pins for debug remain in the design. Taking them out would change the design characteristics and require a new round of debug.

    6. Chipscope 6 Another customer option for trace during in-circuit debug is an internal logic analyzer with the trace stored using internal memory in the FPGA. A good example is Xilinx ChipScope Pro. Trace is routed out for viewing via JTAG. The JTAG tool that communicates with the FPGA is known by customers as a “cable.” In the internal logic analysis case, limited memory depth and dedicating part of the FPGA memory to debug instead of the design, can limit a designer’s ability to debug effectively. Another customer option for trace during in-circuit debug is an internal logic analyzer with the trace stored using internal memory in the FPGA. A good example is Xilinx ChipScope Pro. Trace is routed out for viewing via JTAG. The JTAG tool that communicates with the FPGA is known by customers as a “cable.” In the internal logic analysis case, limited memory depth and dedicating part of the FPGA memory to debug instead of the design, can limit a designer’s ability to debug effectively.

    7. Chipscope 7 Another customer option for trace during in-circuit debug is an internal logic analyzer with the trace stored using internal memory in the FPGA. A good example is Xilinx ChipScope Pro. Trace is routed out for viewing via JTAG. The JTAG tool that communicates with the FPGA is known by customers as a “cable.” In the internal logic analysis case, limited memory depth and dedicating part of the FPGA memory to debug instead of the design, can limit a designer’s ability to debug effectively. Another customer option for trace during in-circuit debug is an internal logic analyzer with the trace stored using internal memory in the FPGA. A good example is Xilinx ChipScope Pro. Trace is routed out for viewing via JTAG. The JTAG tool that communicates with the FPGA is known by customers as a “cable.” In the internal logic analysis case, limited memory depth and dedicating part of the FPGA memory to debug instead of the design, can limit a designer’s ability to debug effectively.

    8. Chipscope 8 Choose the Core that Best Meets Your Design Requirements

    9. Chipscope 9 Debug Logic Anywhere Within the FPGA

    10. Chipscope 10 ChipScope Pro Tools Allow You to Add Cores at Any Time in the Design ChipScope Pro Core Generator Generate and add cores at the beginning of the design process ChipScope Pro Core Inserter Target existing signals and generate and insert cores into a synthesized design ChipScope Pro configuration Simplify iterative debug and verification process

    11. Chipscope 11 ChipScope Pro Interface Makes FPGA Debug Easy

    12. Chipscope 12 Remote Debug and Verification

    13. Chipscope 13 Measures new groups of internal FPGA signals in seconds without Recompiling the design Impacting the timing of the design Save 15 min to 10 hours per new measurement Achieves wider internal visibility over a fixed number of pins 64 internal probe points for every pin conserves FPGA resources Save 8 hours per problem by not having to create a testbench Eliminates error prone & time consuming tasks Automates signal/bus labeling from FPGA design to logic analyzer Automatically maps FPGA pins from board layout to logic analysis channels Save 2 to 30 minutes per new measurement Exclusive Capability Combines On-Chip Debug with External Logic Analysis Where these capabilities really make a difference for designers is in the time saved during the development process. This slide highlights some actual perspectives shared by an FPGA designer who had the opportunity to evaluate and comment on the potential for this tool to contribute to his productivity. His comments reflect his experiences over a number of FPGA development projects. To illustrate the potential contribution, we’ve highlighted his observations about potential time saved in each of the key areas discussed in the previous slide. The first area of dynamic probing (changing internal probe points) offers the potential for major time savings, especially when a design is heavily constrained such that it requires long recompile times. The second area (wider internal visibility) potentially allows a measurement approach to be used rather than a simulation/testbench approach, according to this designer. This means the designer can get right to the integration task at hand, and bypass the time consuming steps required to exhaustively simulate the design. And finally, the convenience of having the logic analyzer connections automatically synched with the FPGA design tool is a real help, not just in time (although it’s significant as shown here) but in making sure that the designer understands clearly what he or she is seeing in the logic analysis environment. Where these capabilities really make a difference for designers is in the time saved during the development process. This slide highlights some actual perspectives shared by an FPGA designer who had the opportunity to evaluate and comment on the potential for this tool to contribute to his productivity. His comments reflect his experiences over a number of FPGA development projects. To illustrate the potential contribution, we’ve highlighted his observations about potential time saved in each of the key areas discussed in the previous slide. The first area of dynamic probing (changing internal probe points) offers the potential for major time savings, especially when a design is heavily constrained such that it requires long recompile times. The second area (wider internal visibility) potentially allows a measurement approach to be used rather than a simulation/testbench approach, according to this designer. This means the designer can get right to the integration task at hand, and bypass the time consuming steps required to exhaustively simulate the design. And finally, the convenience of having the logic analyzer connections automatically synched with the FPGA design tool is a real help, not just in time (although it’s significant as shown here) but in making sure that the designer understands clearly what he or she is seeing in the logic analysis environment.

    14. Chipscope 14 Compatibility Xilinx FPGAs Virtex-4 Virtex-II Pro Virtex-II Spartan-3E Spartan-3 Agilent Logic Analyzers 1680-series 1690-series 16900-series with following modules: 16740 series 16750 series 16910 series 16950 series

    15. Chipscope 15 Xilinx ChipScope Pro Enabling Complete FPGA Debug Solutions Xilinx ChipScope Pro debug and verification solutions address many of the challenges faced by FPGA designers today. Increased capabilities such as IBA, VIO and ATC provide users with cost effective tools for on-chip system debug of complex systems. Xilinx ChipScope Pro debug and verification solutions address many of the challenges faced by FPGA designers today. Increased capabilities such as IBA, VIO and ATC provide users with cost effective tools for on-chip system debug of complex systems.

    16. Chipscope 16 What’s Next View the ChipScope Pro product demo online Learn how to insert ChipScope Pro cores into a design Learn how to use the ChipScope Pro analyzer to debug and verify

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