The Structure of the CPU

1. The Structure of the CPU

2. The structure of the CPU At the top level, the computer consists of the CPU, memory and I/O components These components are interconnected in some fashion to achieve the basic function of the computer which is to execute programs Virtually all contemporary computers are based on an concepts developed by John Von Neumann. The design is referred to as the Von Neumann Architecture It is based on 3 key concepts Data and instructions are stored in a single read-write memory The contents of these memory are addressable by location Execution is in a sequential fashion from one instruction to the next (unless explicitly specified otherwise)

3. The structure of the CPU The CPU hardware is designed to perform a finite set of arithmetic and logic functions on input data e.g. add, compare, store, read, multiply etc. The particular function that has to be performed is determined by control signals. Hence control signals tell each component what it has to do Hence a program can be seen as a sequence of control signals Machine instructions are usually termed as opcodes An opcode can be viewed as representing on or more control signals

4. The structure of the CPU Figure one shows a digital electronic circuit that always does the same thing on the data For instance if it is an addition circuit, the data can be two values to be added, the output is the results of the addition This can also be seen as a program but it is a hardwired program Figure1: Hard Wired Program

5. The structure of the CPU Different opcodes lead to generation of control different signals What the Digital electronic circuit does with the data is determined by the control signals The sequence of opcodes can be seen as a software program Figure 2: Software Program

6. The structure of the CPU The two components shown in figure 2 constitute the CPU The top component can be viewed as the control unit The lower component as the arithmetic and logic unit Several other components are needed to yield a functioning computer I/O Components Inputs components are for entering data into the system and instructions Output components are for reporting the results of the system Main memory for storage of data and instructions

7. Figure 3: Main Computer Components

8. The structure of the CPU Registers PC – Program counter IR – Instruction Register MAR – Memory Address Register MBR – Memory Buffer Register I/O AR – I/O Address register I/O BR – I/O Buffer Register

9. The structure of the CPU The CPU exchanges Data with memory To do this, it makes use of two internal registers MAR and MBR MAR specifies the location (Address) in memory from which data is to be read or written MBR contains data to be written to memory or read from memory To exchange data with I/O devices, the CPU uses two registers: I/O AR and I/O BR I/O AR specifies the I/O device (by specifying an I/O address) of one of the buffers I/O BR contains data to be read from an I/O buffer or to be written into an I/O buffer specified by I/O BR

10. The structure of the CPU The PC (program counter) contains the address of the next instruction. This is the instruction that will be executed after the current instruction is completed (unless the current instruction specifies a jump) Note the difference btn an instruction and the address of the instruction The memory module consists of a set of memory locations These locations are identified by sequentially numbered addresses Each location contains a binary number that can be interpreted as either an instruction or data

11. Instruction Fetch and Execute The basic function of the computer is execution of a program which consists of a set of instructions stored in memory In its simplest form, instruction processing consists of 2 steps Fetch – The processor reads instructions from memory one instruction at a time Execution – instruction execution may involve several operations. This will depend on the nature of the instruction itself The processing required for a single instruction is called instruction cycle The two steps are referred to as the fetch cycle and the execute cycle

12. Instruction Fetch and Execute Fetch Cycle At the beginning of each instruction cycle, the processor holds the address of the next instruction to be fetched. This address is loaded into the MAR and the value in the PC is incremented by 1 For instance if the PC contains the value 300, the address loaded in MAR is 300, and the value of PC becomes 301 Placing of the address in MAR and activation of a read control signal results in the value in memory address 300 being transferred to AR via the MBR This completes the Fetch cycle.

13. Instruction Fetch and Execute Fetch Cycle Assuming that instruction occupies a 16 bit word, then some bits will be reserved for the opcode, and the other bits for the address of the operand(s) 300 Figure 4: A memory word containing an instruction. We can have up to 16 unique opcodes and up to 212 unique memory addresses Figure 5: A memory word containing an Integer

14. Instruction Fetch and Execute Execute Cycle The opcode section of the instruction specifies the actions that are to be performed These actions/operations fall in 4 categories Processor-Memory – data may be transferred from memory to processor or processor to memory Processor-I/I – Data may be transferred from I/O to processor or from processor to I/O Data processing – The processor may perform some arithmetic or logic operations on the data Control – e.g. a Jump instruction which specifies that the sequence of execution to be altered

15. The Arithmetic and Logic Unit (ALU) The ALU It is the subsystem where all processing takes place in the computer It has registers which are used for temporally storage of information The information in the registers is worked on by the processing components e.g. the adder

16. The Arithmetic and Logic Unit (ALU) The registers in the ALU have to hold all the information processed by the computer In particular, they have to Accepts and hold the operands for the various arithmetic and logic instructions that the machine can perform The operands will generally be provided by the memory unit Hold and transmit the results of the operations These will generally have to be sent to the memory unit Retain intermediate results (from earlier operations) for use in subsequent operations

17. The Arithmetic and Logic Unit (ALU) The registers will therefore need to be connected to each other; Connected to the units in the ALU that perform the processing Connected to units outside the ALU The following are the main units in the ALU MDR – Memory Data Register Accumulator Register - A Multiplier Quotient Register (MQ) The adder

18. The Arithmetic and Logic Unit (ALU) MDR The only means of communication between the ALU and memory Connected to the MBR Used as an intermediate stage in the transfer of data from memory to any register in the ALU Used to hold the second operand for all binary operations Augend (the value that is added to) for addition Minuend (the value that is subtracted from) for subtraction Multiplier for multiplication Divisor for division

19. The Arithmetic and Logic Unit (ALU) Accumulator Used for holding the first operand for binary operations Added (the value that is added) for addition Subtrahend (the value that is subtracted) for subtraction Multiplicand for multiplications Dividend for division It also accepts the results for most arithmetic operations Sum for addition Difference for subtraction Part of the product for multiplication Remainder for division

20. The Arithmetic and Logic Unit (ALU) Accumulator … The accumulator is a double rank register Main (lower rank) register Buffer (upper rank) register The output of the adder is connected to the buffer register The main register is connected to adder as one of the source of inputs to the adder Hence the added can be held in the main register, and the result (sum) stored in the buffer register

21. The Arithmetic and Logic Unit (ALU) Accumulator … The accumulator is a shift register where numbers can be shifted right or left, or scaled up or down Hence the ithbit is gated to bits: i , i-1 and i+1. Shifting involves copying the contents of the main register one bit into the left or right in the buffer register, then copying the contents of the buffer register into the main register i.e. shifting cannot be accomplished by merely copying bit i in main register into bit i+1 in the main register because bit i might be replaced by bit i-1 before it is copied into bit i+1 In tandem with the MQ, it accumulates the product in multiplication, and holds the dividend for division It retains the remainder at the end of the division operation

22. The Arithmetic and Logic Unit (ALU) Multiplier Quotient Is also a double rank register It has a similar structure as the accumulator except that it is not connected to the adder Independently, or in tandem with the accumulator, it can be used to shift numbers to the left or to the right It is used to hold the multiplier Used together with the accumulator to hold the product in multiplication, and hold the dividend in division In case of division, it is used to form the quotient

23. The Arithmetic and Logic Unit (ALU) Shift Counter (SC) Keeps count of the number of shifts performed in case of shift left, shift right, multiply and divide operations Status Flip-flops overflow – set when there is an overflow during addition or subtraction Divide fault – set if the divisor is not larger in magnitude than the dividend Sign-compare – if the signs of the two operands in addition, subtraction, multiplication and division are not the same

24. The Arithmetic and Logic Unit (ALU) Adder and Logic Processor Used in all arithmetic and logic operations and performs the following functions Accepts input from the MDR and the accumulator and supplies its output (the sum or difference) to the Accumulator buffer This is necessary for addition, subtraction, multiplication and division Used for complementing numbers It has facilities for transferring carries from the less significant to the more significant stages Has facilities for logical operations

25. Interconnection Structures A computer consists of components (Modules) of three basic types Processor Memory I/O These components need to communicate with each other Hence there must be pathways for connecting the components The collection of paths connecting the various components is called the interconnection structure

26. Interconnection Structures Forms of Input and Output for Each Module Memory Typically consists of N words of equal length Each word is assigned a unique numerical address from 0 to N-1 A word of data can be read or written into memory The nature of the operation is indicated by read and write control signals The location of the operation is specified by an address Note that there can be several memory modules

27. Interconnection Structures Forms of Input and Output for Each Module I/O module From an internal (computer) point of view, I/O functions in a similar way to memory There are two operations: read and write An I/O module may control more than one external device We can refer to each of the interfaces to an external device as a port and give each a unique address i.e. 0,1, …M-1 An I/O module may be able to send interrupt signals to the processor The I/O module has data paths for communicating with the external device it controls Note that there can be several I/O modules

28. Interconnection Structures Forms of Input and Output for Each Module Processor Reads in instructions and data Writes out data after processing Uses control signals to control the operations of the entire system Receives interrupt signals

29. Interconnection Structures Types of transfers Memory to processor: the processors reads an instruction or unit of data from memory Processor to memory: the processor writes a unit of data to memory I/O to processor: the processor reads data from an I/O device via an I/O module Processor to I/O: the processor sends data to an I/O device via an I/O module I/O to or From memory: An I/O module is allowed to exchange data directly with memory without going through the processor using direct memory access (DMA)

30. Interconnection Structures Figure 6: Bus interconnection Scheme

31. Interconnection Structures A bus is a communication pathway connecting two or more devices A key characteristic is that it is a shared transmission medium Only one device can transmit at a given time A bus typically consists of 50 to hundreds of separate lines The lines can be classified into three functional groups Data lines Provide a pathway for moving data btn the modules collectively called the data bus May consist of 8 to hundreds of lines The number of lines is called the width of the data bus

32. Interconnection Structures The wider the data bus, the more the number of bits that can be sent at once. For instance a bus with 8 lines will require two clock cycles to transfer a data word of 16 bits Hence it has an effect on performance The Address Lines (Address bus) Used to designate the source or destination of the data on the data bus For instance, it the processor wishes to read the data in a given word in memory, it puts the words address in the address bus The greater the width of the address bus, the more the number of address we can access. Hence the width determines the maximum possible memory capacity

33. Interconnection Structures The same lines are also used to address the I/O ports The control lines Use to control the access to, and the use of the data and address lines Because the data and address lines are shared, there must be some form of control of their use Control lines transmit both command and timing information btn the system modules Timing signals indicate the validity of the data and address information, command signals specify operations to be performed

34. Interconnection Structures Some control signals Memory write: Causes data on the bus to be written on the addressed location Memory read: causes data on the addressed memory location to be placed on the bus I/O write: causes data on the bus to be output on the addressed memory port I/O read: causes data on the addressed I/O port to be placed on the bus Bus request: Indicates that a module needs to gain control of the bus Bus grant: indicates that the requesting module has been granted control of the bus

35. Interconnection Structures Some control signals Interrupt request: indicates that an interrupt is pending Interrupt ACK: acknowledges that the pending interrupt has been recognized Clock: used to synchronize operations Reset: initialize all modules The operation of the bus is as follows: If one module wishes to send data to another, it must do two things Obtain use of the bus Transfer data via the bus

36. Interconnection Structures If one module wishes to request data from another module it must Obtain use of the bus Transfer the request to the other module via the appropriate control and address lines It must then wait for the other module to send the data