Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics
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Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics. I. O'Connor , K. Jabeur, D. Navarro, N. Yakymets Lyon Institute of Nanotechnology, Lyon, France P.E. Gaillardon, M.H. Ben Jamaa, F. Clermidy CEA-LETI-MINATEC, Grenoble, France. nano.grain. Outline.

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Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics

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Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics

Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics

I. O'Connor, K. Jabeur, D. Navarro, N. Yakymets

Lyon Institute of Nanotechnology, Lyon, France

P.E. Gaillardon, M.H. Ben Jamaa, F. Clermidy

CEA-LETI-MINATEC, Grenoble, France

nano.grain


Outline

Outline

  • Some technology fabric considerations

  • Logic cells

    • Reduced-complexity dynamic standard cells

    • Reconfigurable logic cells and design methods

  • Interconnect strategies

    • Matrix topologies

    • Island-style architecture

    • Metrics and comparisons

  • Conclusions


Explaining the jargon

Explaining the jargon

  • nanoscale computing fabric (nanoFabric):

    • nanoFabric: an array of connected nanoscale logic blocks (nanoBlocks)

    • nanoBlock: a circuit block containing programmabledevices to compute boolean logic functions and means to route data

  • usually hybrid approach (silicon die, or CMOS compatible):

    • bottom-up structure: chemical self-assembly for dense and regular arrangement of elements

    • top-down structure: conventional process options for interconnect or for computation

    • and memory …


Double gate ambipolarity

G

PG

state

+V

+V

on (n)

-V

+V

off (n)

+V

-V

off (p)

-V

-V

on (p)

X

0

off (n/p)

Double-gate ambipolarity

  • In DG-CNTFETS, the Id-Vg characteristic demonstrates ambipolarity

    • Vbg > 0V:

      device behavior = n-type FET

    • Vbg < 0V:

      device behavior = p-type FET

    • Vbg floating / 0V:

      device is in the off state

  • Verilog-A model developed (IMS)

  • Reduced-complexity logic cells

  • Ultra fine-grain reconfigurable logic cells

Y.-M. Lin et al., IEEE Trans. Nanotechnology, 4(5),2005


Hybrid technology

Hybrid technology

  • "SelectiveGrowth of Well-AlignedSemiconducting Single-WalledCarbon Nanotubes", L. Ding et al., Nano Lett., 9(2), 800 (2009)

  • "Monolithicintegration of CMOS VLSI and carbon nanotubes for hybridnanotechnology applications", D. Akinwande et al., IEEE Trans. Nanotechnology, 7(5), 636 (2008)


Outline1

Outline

  • Some technology fabric considerations

  • Logic cells

    • Reduced-complexity dynamic standard cells

    • Reconfigurable logic cells and design methods

  • Interconnect strategies

    • Matrix topologies

    • Island-style architecture

    • Metrics and comparisons

  • Conclusions


Dynamic logic standard cells

Vdd

Ev

VbA

A

VbB

B

Y

Pc

gnd

+V

+V

In1

+V

Out

PC

In2

Inn

Dynamic logic standard cells

  • use the extra gate (PG) to reduce complexity

  • function path includes EV phase

  • transistor count:

    • 2n (static logic)

    • n+2 (conventional DL)

    • n+1 (this work)

  • clocking strategy:

    • Double clock (DCK)

    • Multiple clock (MCK)

    • Single clock (SCK)

EV

function path

  • Layoutflipping: rich set of operators


Clocking strategies and cell variants

function path

function path

function path

In2

In1

PC

EV-

Out

+V

+V

In1

In2

Inn

Inn

EV+

Out

+V

+V

Clk

EV

PC

Out

Inn

In2

In1

+V

-V

Clocking strategies and cell variants

  • PUN

  • EV+{0,+V}, EV-{0, -V}, PC{0,+V}

  • mixed N- and P-function path: more complex functions

  • PUN

  • EV{0,+V}, PC{0,+V}

  • Precharge: (PC=+V, EV=0)

  • Evaluation: (PC=0, EV=+V)

DCK

MCK

SCK

  • PDN

  • Clk{0,+V}

  • Precharge:

  • (Clk=0)

  • Evaluation: (Clk=+V)

  • complementary functions


Comparison simulation

Comparison (simulation)

  • Vdd=1V fclk=3GHz, tr=tf=20ps, CL=150aF

  • av. power +(0-20)%

  • wc. delay -(30-50)%

    • no EV transistor, lower branch resistance

  • pdp –(25-40)%


Reconfigurable logic cell cnt dr7t

Vdd

VbgA

VbgB

VbgC

Y

+V

+V

+V

A+B

EV1

PC2

+V

+V

-V

A+B

Y

+V

-V

+V

A.B

+V

-V

-V

A+B

A

VbA

VbB

B

VbC

-V

+V

+V

A.B

-V

+V

-V

A+B

C

-V

-V

+V

A.B

PC1

EV2

-V

-V

-V

A.B

+V

0

+V

A

+V

0

-V

A

0

+V

+V

B

0

+V

-V

B

1

0

0

0

0

0

-V

0

PC1

EV1

PC2

EV2

C

f(A,B,VbA,VbB)

Y

f(C,VbC)

t

Reconfigurable logic cell CNT-DR7T

 = 1.5nm

Ioff = 10-13A

Ion/Ioff=105

J. Liu, I. O'Connor, D. Navarro, F. Gaffiot,

El. Lett., 43(9), April 2007

  • boolean data inputs A and B, data output Y {0,+V)

  • four-phase non-overlapping clock signals PC1, PC2, EV1, EV2 {0,+V)

  • ternary configuration inputs VbgA, VbgB, VbgC{-V,0,+V)


Towards complete operator sets

Towards complete operator sets

DRLC-6T

15 functions

DRLC-9T

16 functions

  • 1.5X-2X decrease in power consumption

  • more functions, fewer transistors, one extra configuration signal


Outline2

Outline

  • Some technology fabric considerations

  • Logic cells

    • Reduced-complexity dynamic standard cells

    • Reconfigurable logic cells and design methods

  • Interconnect strategies

    • Matrix topologies

    • Island-style architecture

    • Metrics and comparisons

  • Conclusions


Physical view clusters of matrices

Physical view: clusters of matrices


Directed matrix interconnect topologies

Directed matrix interconnect topologies

B

logic function

Banyan_4d4w

frc

configuration inputs

Y

Y

data output (x2)

Baseline_4d4w

A

data inputs

Mod_Omega_4d4w

Flip_4d4w


Mapping success rate for matrices

Mapping success rate for matrices

[email protected]

omega topology can achieve up to 25% more functions

[email protected]

[email protected]

[email protected]

% exploitable cases

0-fault omega

0-fault banyan

0-fault baseline

0-fault flip


Towards undirected topologies

Towards undirected topologies

f11

f11

f11

f12

f12

f12

f21

f21

f21

f22

f22

f22

Banyan

Systolic array

Cross-cap


When to move to island style

When to move to island-style?

1-bit FA application

Island-style

Cell-matrix


Wrap up

Wrap-up

  • Logic with ambipolar DG-CNTFETS:

    • reduced-complexity dynamic-logic standard cells with –(25-40)% PDP

    • complete operator set dynamic-logic reconfigurable cells with low transistor count and power consumption

  • Interconnect strategies:

    • directed matrix interconnect topology exploration

    • cross-cap topology proposed to relieve latency and data-directivity issues

    • matrices within islands allow efficient packing

    • routing between islands to be explored …


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