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National Sun Yat-sen University Embedded System Laboratory Progress Report

National Sun Yat-sen University Embedded System Laboratory Progress Report. Presenter : Jiun-Cheng Ju. Progress of Jiun -Cheng Ju. Current progress AXIChecker Design Add AHB slave interface(done) AXIChecker analyzer(done) Verification

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National Sun Yat-sen University Embedded System Laboratory Progress Report

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  1. National Sun Yat-sen University Embedded System LaboratoryProgress Report Presenter :Jiun-Cheng Ju

  2. Progress of Jiun-Cheng Ju • Current progress • AXIChecker • Design • Add AHB slave interface(done) • AXIChecker analyzer(done) • Verification • Modify SystemVerilog example to generate simple random pattern • GUC • Add HPChecker to Gprime platform • Problem : Quartus II 3.0 not support Gprime FPGA board • Solution : Use Quartus II 7.2 to synthesize and download to Gprime FPGA board

  3. Next Progress • AXIChecker • Verifycation • Generate random pattern pattern to verify AXIChecker rules case by case. • GUC • Test HPChecker function on Gprime FPGA board • Run C test program • 3Dchip integration • Check AHB protocol on FPGA platform • Dump HPChecker’s reference table

  4. GPrime top module architecture HPChecker S

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