National Sun Yat-sen University Embedded System Laboratory

1. National Sun Yat-sen University Embedded System Laboratory Functional Verifications for SoC Software/Hardware Co-Design: From Virtual Platform to Physical Platform IEEE international, SoC Conference (SOCC) Yi-Li Lin and Alvin W.Y. Su Presenter: Ming-Shiun Yang 2012/06/24

2. Abstract This paper applies heterogeneous simulation to achieve system and functional level co-verification throughout SoC design flow. It reduces high verification complexity resulted from covering software and hardware works and involving various tools. Stubsfor data transport and a Verification Router for heterogeneous simulation management are proposed. A functional module is transformed from a highly abstract model to its target design progressively through a series of intermediate models. Those models can be validated as a portion of a complete SoC system model. The proposed heterogeneous verification is demonstrated with a jpeg encoder.

3. Related Work QEMU (Instruction set simulator) FPGA platform [19] HDL Simulator RTL Module Connects to PC via USB Emulate a full system SystemC Hardware Model Full verification for SoC SW/HW co-design

4. What’s the problem • Most the related works do not cover a whole SoC design flow(co-simulation involves various tools). Figure 1：AConventional SoC Design Flow.

5. Proposed-Verification Router • Verification Router • A centralized manager System model Virtual platform HW model RTL design Physical platform

6. Proposed-Stubs • Stubs • For data exchange • With the same communication protocol • Shared memory • Environment can be : • System Model • Hardware Model • HDL • FPGA • Blocks can be : • HW/SW model or module …

7. Example(1) • System model and Hardware model co-simulation. HOST Host SystemC QEMU Hardware Model QEMU_Stub HW_SystemC_stub 2. signal Memory Shared Memory 1. Data and target address 3. Data and target address 7

8. Example(2) • Hardware model and HDL co-simulation. Hardware SystemC Model RTL Model target address and Data TLM interface SystemC_stub HDLSim_Stub (SystemC model) AMBA or others protocol

9. Example(3) • Hardware model and FPGA co-simulation. SMIMS APIs SMIMS FPGA SystemC Module Data transport wrapper SC_FPGA_stub Data exchange • SMIMS APIs：FIFODataWrite and FIFODataRead

10. Example(4) • System model and HDL/FPGA co-simulation. QEMU SMIMS APIs FPGA HDLSim_ Stub RTL Module Data exchange AMBA or others protocol

11. Demonstration with jpeg encoder • Run a JPEG encoding application on Android emulator • QEMU - ARM system with Linux Exchanged data and verified result Android emulator

12. Conclusion • This paper proposed • Stubswith the same communication protocol for data transport. • Verification Router to connect different tools in ESL design for co-verification.

13. My Common • The flow of SoC design is clearly. • The paper do not present the corresponding figure of heterogeneous simulation so that it is difficult to understand.