Comp541 memories ii drams
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COMP541 Memories II: DRAMs PowerPoint PPT Presentation


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COMP541 Memories II: DRAMs. Montek Singh Mar 2, 2010. Topics. Random-Access Memory Dynamic. Dynamic RAM. Capacitor can hold charge Transistor acts as gate No charge = ‘0’ Can connect switch & add charge to store a ‘1’ Then disconnect switch Can read by connecting switch Sense amps.

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COMP541 Memories II: DRAMs

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COMP541Memories II:DRAMs

Montek Singh

Mar 2, 2010


Topics

  • Random-Access Memory

    • Dynamic


Dynamic RAM

  • Capacitor can hold charge

  • Transistor acts as gate

  • No charge = ‘0’

  • Can connect switch & add charge to store a ‘1’

  • Then disconnect switch

  • Can read by connecting switch

    • Sense amps


DRAM Bit Cell

  • Contrast w/ SRAM

SRAM bit cell:

DRAM bit cell:

5-<4>


Hydraulic Analogy

Storage

Full (1)

Empty (0)

Pump fills tank to 1 value

Pump drains tank to 0 value


Reading

Outside water begins at intermediate level (black wavy line)

Tank had a 1 value – raises water level

Tank had a 0 value – lowers water level


DRAM Characteristics

  • Destructive Read

    • When cell read, charge removed

    • Must be restored after a read

  • Refresh

    • Also, there’s steady leakage

    • Charge must be restored periodically


DRAM Logical Diagram


DRAM Read Signaling

  • Lower pin count by using same pins for row and column addresses

Delay until data available


DRAM Write Timing


DRAM Refresh

  • Many strategies

  • Logic on chip

  • Here a row counter


Timing

  • Say need to refresh every 64ms

  • Distributed refresh

    • Spread refresh out evenly over 64ms

    • Say on a 4Mx4 DRAM, refresh window for row 64ms/4096=15.6 us

    • Total time spent is 0.25ms, but spread

  • Burst refresh

    • Same 0.25ms, but all at once

    • May not be good in a computer system

  • Refresh takes low % of total time


Bidirectional Lines

  • Many chips have one set of data pins

  • Used as input for write

  • As output for read

  • Tri-state

  • Makes sense because don’t need both at once


Page Mode DRAM

  • DRAMs made to read & write blocks

  • Example

    • Assert RAS, leave asserted

    • Assert CAS multiple times to read sequence of data

  • Similar for writes


Synchronous DRAM (SDRAM)

  • Has a clock

  • Common type in PCs late-90s

    • Typical DRAMs still synchronous

  • Multiple banks

  • Pipelined

    • Start read in one bank after another

    • Come back and read the resulting values one after another


Read with Autoprecharge


Basic Mode of Operation

Address

Row

Column

RAS

CAS

Data

Data

  • Slowest mode

  • Uses only single row and column address

  • Row access is slow (60-70ns) compared to column access (5-10ns)

  • Leads to three techniques for DRAM speed improvement

    • Getting more bits out of DRAM on one access given timing constraints

    • Pipelining the various operations to minimize total time

    • Segmenting the data in such a way that some operations are eliminated for a given set of accesses


Nibble (or Burst) Mode

RAS------------------------------------

CASCASCASCAS

RACA

D1D2D3D4

  • Several consecutive columns are accessed

  • Only first column address is explicitly specified

  • Rest are internally generated using a counter


Fast Page Mode

RAS------------------------------------

CASCASCASCAS

RACA1CA2CA3CA4

D1D2D3D4

  • Accesses arbitrary columns within same row

  • Static column mode is similar


EDO Mode

RAS------------------------------------

CASCASCASCASCASCASCAS

RACA1CA2CA3CA4CA5CA6CA7

D1D2D3D4D5D6

  • Arbitrary column addresses

  • Pipelined

  • EDO = Extended Data Out

  • Has other modes like “burst EDO”, which allows reading of a fixed number of bytes starting with each specified column address


DRAM on NEXYS2 Board

  • Relatively small at 128Mbits

    • 8M X 16

  • Internal refresh

  • Supports pipelining

  • Bidirectional data lines, full set of address lines

  • Async (right) and sync modes

    • Page, burst

    • 70ns read cycle time

  • http://download.micron.com/pdf/datasheets/psram/128mb_burst_cr1_5_p26z.pdf


DDR DRAM

  • Double Data Rate SDRAM

  • Transfers data on both edges of the clock

  • Currently popular

  • Attempt to alleviate the pinout problems


RAMBUS DRAM (RDRAM)

  • Another attempt to alleviate pinout limits

  • Many (16-32) banks per chip

  • Made to be read/written in packets

  • Up to 1200MHz bus speeds

    • XDR – 8 bits per clock, 16-bit wide bus, 6.4GB

    • But DDR doing very well also


DRAM Controllers

  • Very common to have chip/module that controls memory

    • Handles banks

    • Handles refresh

  • Multiplexes column and row addresses

    • RAS and CAS timing

  • Northbridge on PC chip set


Conclusions

  • RAMs with different characteristics

    • For different purposes

  • Static RAM

    • Simple to use, small, expensive

    • Fast, used for cache

  • Dynamic RAM

    • Complex to interface, largest, cheap

    • Needs periodic refresh


Links

  • Ram Guides (not very technical)

    • http://arstechnica.com/paedia/storage.html

  • DRAM on XSA-100 board

    • http://www.hynix.co.kr/datasheet/pdf/dram/(2)HY57V281620A(L)T-I.PDF


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