Characteristic Presentation

1. Characteristic Presentation Infrastructure design & implementation of MIPS processors for students lab based on Bluespec HDL Students: Danny Hofshi, Shai Shachrur Supervisor: MonyOrbach Winter 2012

2. Lab Vision • The student performing the lab will understand a MIPS processor, • The student will have the tools for performance analyzing of a particular MIPS. • He will implement & evaluate different types of architecture improvements. • He will sense the advantages of various improvements without being concerned with the technical aspects of handling the experiment setup.

3. FPGA C++ BluespecScemi Bluespec HDL

4. Assumptions • The students attending the lab are already familiar with basic aspects of logic design & MIPS architecture. • The students will receive complementary knowledge relevant for the experiment.

5. staff • Academic supervisor: YoavEtsion. • Project supervisor: MonyOrbach. • Project coordinator: Eli Shushan. • Application engineering: Inna Rivkin.

6. Abstract The lab we aspire to create is in respect to a course performed by Dr Derek Chiou from the university of Texas at the recent summer semester. Using new features of the Bluespec HDL and its environment we are able to create a lab setup that enables the student to easily understand & experience processors architecture and performances. The Hardware and software will be described in details in the next slides.

7. Work Flow

8. Lab staff Danny & Shai Project Characterization performance questions & Program for testing Multi cycle MIPS hardware Test, Sync & Conclusions Adjusting the experiment flow Designing the MIPS improvements Running a pilot group

9. Lab staff Danny & Shai Project Characterization performance questions & Program for testing Multi cycle MIPS hardware Test, Sync & Conclusions Part A Adjusting the experiment flow Designing the MIPS improvements Running a pilot group Part B

10. Lab staff Danny & Shai Project Characterization performance questions & Program for testing Multi cycle MIPS hardware Test, Sync & Conclusions Adjusting the experiment flow Designing the MIPS improvements Running a pilot group

11. The basic MIPS architecture The purpose of the below MIPS is to use as a basis for improvements during the experiment. The improvements will be: Pipelining, Branch prediction & Cache • the MIPS will be multi cycle.(3-4 cycles) • Instruction & data memory will be multi cycle. • When instruction is not available, the processor will be in idle. • When performing load word operation from the data memory the processor will be in idle until data is retrieved. • The system will have Ability to control the clock frequency. • MIPS Performance counter will be linked to a C++ environment.

12. MIPS Components • BlueSpec • S C E M I • - PCIe • Clk control Communicating with a c++ environment using generic interface BlueSpec BSV Wrapper BSV Wrapper Xilinx BRAM (Verilog) Xilinx BRAM (Verilog)

13. Lab staff Danny & Shai Project Characterization performance questions Program for testing Multi cycle MIPS hardware Test, Sync & Conclusions Part A Adjusting the experiment flow Designing the MIPS improvements Running a pilot group Part B

14. Performance questions • What are the performances we would like to capture ? • What is the structure and what are the units we would like to display the performance details with ? • Which program to run for the above performance analyzing ? • Will it be a single program or several programs ? • …

15. Lab staff Danny & Shai Project Characterization performance questions Program for testing Multi cycle MIPS hardware Test, Sync & Conclusions Part A Adjusting the experiment flow Designing the MIPS improvements Running a pilot group Part B

16. Test sync & conclusions • Running the test program. • Checking the performance counters. • Modifying the simulation environment appereance.

17. Lab staff Danny & Shai Project Characterization performance questions Program for testing Multi cycle MIPS hardware Test, Sync & Conclusions Part A Adjusting the experiment flow Designing the MIPS improvements Running a pilot group Part B

18. MIPS improvements • Pipeline. • Cache. • Branch prediction. • Discussion: How we would like the students to implement the improvements ? • Will he get a ready made Bit streams ? • Will he get a partial implemented code and will complete the code by himself ?

19. Lab staff Danny & Shai Project Characterization performance questions Program for testing Multi cycle MIPS hardware Test, Sync & Conclusions Part A Adjusting the experiment flow Designing the MIPS improvements Running a pilot group Part B

20. Experiment flow • A-Z experiment booklet. • Preparation report. • complementary knowledge references. • Video ? (By Derek Chiou)

21. Lab staff Danny & Shai Project Characterization performance questions Program for testing Multi cycle MIPS hardware Test, Sync & Conclusions Part A Adjusting the experiment flow Designing the MIPS improvements Running a pilot group Part B

22. We implement Meow prediction ? Pilot group

23. Focus on us Shai & Danny

24. Project Goals • Part A: Creating the Laboratory working environment. • Hardware environment – RTL , interface to outer world ( pci - express ), Xilinx utilities. • Software environment – simulation of a MIPS processor on the above RTL using simplified commands, the same environment will be used for emulation and simulation. • Part B: Designing 3 different MIPS improvements which will work on the same environment, DFT, performance counters. We will implement In separate: • Pipeline • Branch prediction. • Cash

25. Hardware environment • The MIPS Processor will be implemented on a Xilinx Virtex-5 FPGA development board. • DUT integration with a PC will be implemented using a PCIe bus. • untimed TB vs. cycle accurate DUT. • Bit stream loading through a Jtag connection. • Lab students will run the experiment on a Linux O.S using executable SCEMI commands ( supported by Bluespec environment).

26. Hardware Linux Environment PCIe cable Virtex 5 FPGA

27. Software environment Simulation: • Simple “Build” scripts will execute a complete simulation flow. (compile, link, burn, code loader , simulate, results view) • TCP protocol replaces PCIe bus in simulation. • simulation & emulation will have the same structure & units of results for all the tested processors.

28. Software environment At the background: • The MIPS processor will be written using BlueSpec HDL. • Memory blocks using Xilinx native BRAM Bluespec modules. • SCEMI: a generic protocol will connect between a C++ simulation environment to the DUT. • Ability to access MIPS Imemory and Dmemory (R/W) from the PC environment. • NOTE: BlueSpec & PlanAhead (Xilinx compiler) versions need to be pre determined. Any changes in the compilers versions will probably cause problems.

29. Declarations • We set software versions to be: PlanAhed Version 14.1, BlueSpec 2011.06.D redhat Linux running tcsh shell

30. Discussion

31. Gantt Chart Part-A Part -B PNR