EENG 449bG/CPSC 439bG Computer Systems Lecture 17 Memory Hierarchy Design Part I. April 7, 2005 Prof. Andreas Savvides Spring 2005 http://www.eng.yale.edu/courses/2005s/eeng449b. µProc 60%/yr. 1000. CPU. “Moore’s Law”. 100. Processor-Memory Performance Gap: (grows 50% / year).
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EENG 449bG/CPSC 439bG Computer SystemsLecture 17Memory Hierarchy Design Part I
April 7, 2005
Prof. Andreas Savvides
Performance Gap:(grows 50% / year)
1st Alpha: 340 ns/5.0 ns = 68 clks x 2 or136
2nd Alpha:266 ns/3.3 ns = 80 clks x 4 or320
3rd Alpha:180 ns/1.7 ns =108 clks x 6 or648
Processor % Area %Transistors
Disk, Tape, etc.
Selects the set
Selects the desired data from the block
Compared against for a hit
While in cache
AMATHarvard=75%x(1+0.64%x50)+25%x(1+6.47%x50) = 2.05
Performance with cache misses
Four main categories of optimizations
- multilevel caches, critical word first, read miss before write miss, merging write buffers and victim caches
- larger block size, larger cache size, higher associativity, way prediction and pseudoassociativity and computer optimizations
2. Reduce the miss penalty or miss rate via parallelism
- non-blocking caches, hardware prefetching and compiler prefetching
3. Reduce the time to hit in the cache
- small and simple caches, avoiding address translation, pipelined cache access
3) Change Compiler:
Which of 3Cs is obviously affected?
What else drives up block size?
Flaws: for fixed block size
Good: insight => invention