ECE 551: Digital System Design & Synthesis

ECE 551: Digital System Design & Synthesis Lecture Set 10 10.1: Functional & Timing Verification (Separate File) 10.2: Faults & Testing 10.2 Appendix: PODEM Example Slides adapted from ECE 553 Slides by Prof. Kewal Saluja

ECE 551 - Digital System Design & SynthesisLecture 10.2 – Faults and Testing Overview • Introduction • Fault Models • Test Pattern Generation • Design for Testability (DFT) – Serial Scan • Built-In Self-Test (BIST) • Boundary Scan (JTAG/IEEE 1149.1) • Quiescent Drain Current (IDDQ) Testing

Introduction • The manufacturing process for ICs is so complex that only a portion of all chips produced are good – the percentage of such good chips is referred to as the yield • In order to avoid shipping defective products, manufacturing test at the die and packaged chip level is required. • Complex chips => complex tests • The objective: summary the elements of contemporary IC test

Overview • Introduction • Fault Models • Test Pattern Generation • Design for Testability (DFT) – Serial Scan • Built-In Self-Test (BIST) • Boundary Scan (JTAG/IEEE 1149.1) • Quiescent Drain Current (IDDQ) Testing

Common Fault Models • Single stuck-at faults • Transistor open and short faults • Memory faults • PLA faults (stuck-at, cross-point, bridging) • Functional faults (processors) • Delay faults (transition, path) • Analog faults

Stuck-at Faults • Single stuck-at fault model • What does it achieve in practice? • Fault equivalence • Checkpoint faults

Single Stuck-at Fault • Three properties define a single stuck-at fault • Only one line is faulty • The faulty line is permanently set to 0 or 1 • The fault can be at an input or output of a gate • Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults Faulty circuit value Good circuit value j c 0(1) s-a-0 d a 1(0) g h 1 z i 0 1 e b 1 k f Test vector for h s-a-0 fault

Single Stuck-at Faults (contd.) • How effective is this model? • Empirical evidence supports the use of this model • Has been found to be effective to detect other types of faults • Relates to yield modeling • Simple to use

Fault Equivalence • Number of fault sites in a Boolean gate circuit = #PI + #gates + # (fanout branches). • Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. • If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. • Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.

Equivalence Example sa0 sa1 Faults in blue removed by equivalence collapsing sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 20 Collapse ratio = ----- = 0.625 32

Checkpoints • Primary inputs and fanout branches of a combinational circuit are called checkpoints. • Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit. Total fault sites = 16 Checkpoints ( ) = 10

Summary • Gate level models are most prevalent in logic testing • Fault models are analyzable approximations of defects and are essential for a test methodology. • For digital logic single stuck-at fault model offers advantage of effective tools and much experience. • Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests. • Stuck-short and delay faults and technology-dependent faults require special tests. • Memory and analog circuits need other specialized fault models and tests.

Definition of Automatic Test-Pattern Generator • Operations on digital hardware: • Inject fault into sequential circuit modeled in computer • Use various ways to activate and propagate fault effect through hardware to circuit output • Output flips from expected to faulty signal • Scan design – add test hardware to all flip-flops to make them a giant shift register in test mode • Can shift state in, scan state out • Widely used – makes sequential circuit into combinational circuit for testing! • Costs: 5 to 20% chip area, circuit delay, extra pin, longer test sequence

Notation Failing Machine 0 1 0 1 X Good Machine 1 0 0 1 X Symbol D D 0 1 X Meaning 1/0 0/1 0/0 1/1 X/X Roth’s D Algebra

Conditions for Finding a Test • Fault excitation – the signal value at the fault site must be different from the value of the stuck-at fault (thus fault site must contain a D or a D) • The fault effect must be propagated to a primary output (A D or a D must appear at the output) • Some simple observations • There must be at least a D or a D on some circuit nets) • D’s must form a chain to some output

Exhaustive Algorithm • For n-input circuit, generate all 2n input patterns • Infeasible, unless circuit is partitioned into cones of logic, with 15 inputs • Perform exhaustive ATPG for each cone • Misses faults that require specific activation patterns for multiple cones to be tested

Random-Pattern Generation • Flow chart for method • Use to get tests for 60-80% of faults, then switch to D-algorithm or other ATPG for rest

Path Sensitization Method - Example • Fault Sensitization • Fault Propagation • Line Justification

Path Sensitization Method -Example • Try path f – h – k – L. This path is blocked at j, since there is no way to justify the 1 on i 1 D D D D 1 D 0 1 1

Path Sensitization Method • Try simultaneous paths f – h – k – L and g – i – j – k – L. These paths blocked at k because D-frontier (chain of D or D) disappears 1 D D 1 1 D D D 1

Path Sensitization Method Circuit Example • Final try: pathg – i – j – k – L – test found! 0 0 D D 1 D D D 1 1

OverviewMajor ATPG algorithms • Definitions • D-Algorithm (Roth) – 1964-66 • D-cubes • Bridging faults • Logic gate function change faults • PODEM (Goel) -- 1981 • X-Path-Check • Backtracing • Summary

Definition • Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective. • DFT methods for digital circuits: • Ad-hoc methods • Structured methods: • Scan • Partial Scan • Built-in self-test (BIST) • Boundary scan

Scan Design • Objectives • Simple read/write access to all or subset of storage elements in a design. • Direct control of storage elements to an arbitrary value (0 or 1). • Direct observation of the state of storage elements and hence the internal state of the circuit. Key is – Enhanced controllability and observability.

Scan Design • Circuit is designed using pre-specified design rules. • Test structure (hardware) is added to the verified design: • Add one (or more) test control (TC) primary input. • Replace flip-flops by scan flip-flops and connect to form one or more shift registers in the test mode. • Make input/output of each scan shift register controllable/observable from PI/PO. • Use combinational ATPG to obtain tests for all testable faults in the combinational logic. • Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test.

Scan Flip-Flop (master-slave) Master latch Slave latch D TC Q Logic overhead MUX Q SD CK D flip-flop Master open Slave open CK t Normal mode, D selected Scan mode, SD selected TC t

Adding Scan Structure PI PO SFF SCANOUT Combinational logic SFF SFF Not shown: CK or MCK/SCK feed all SFFs (scan Flip-flops). TC or TCK SCANIN

Comb. Test Vectors I2 I1 O2 O1 PI PO Combinational logic SCANIN TC SCANOUT N2 N1 S2 S1 Next state Present state

Comb. Test Vectors I2 Don’t care or random bits I1 PI SCANIN S1 S2 TC 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 O2 O1 PO SCANOUT N2 N1 Sequence length = (nsff + 1) ncomb + nsff clock periods ncomb = number of combinational vectors nsff = number of scan flip-flops

Scan Overhead • IO pins: One pin necessary. • Area overhead: • Gate overhead = [4 nsff/(ng+10nff)] x 100%, where ng = comb. gates; nff = flip-flops; • Example – ng= 100k gates, nff = 2k flip-flops, overhead = 6.7%. • More accurate estimate must consider scan wiring and layout area. • Performance overhead: • Multiplexer delay added in combinational path; approx. two gate-delays. • Flip-flop output loading due to one additional fanout; approx. 5-6%.

BIST Process • Test controller – Hardware that activates self-test simultaneously on all PCBs • Each board controller activates parallel chip BIST Diagnosis effective only if very high fault coverage

BIST Architecture • Note: BIST cannot test wires and transistors: • From PI pins to Input MUX • From POs to output pins

Pattern Generation • Store in ROM – too expensive • Exhaustive • Pseudo-exhaustive • Pseudo-random (LFSR) – Preferred method • Binary counters – use more hardware than LFSR • Modified counters • Test pattern augmentation • LFSR combined with a few patterns in ROM • Hardwarediffracter – generates pattern cluster in neighborhood of pattern stored in ROM

Exhaustive Pattern Generation (A Counter) • Shows that every state and transition works • For n-input circuits, requires all 2n vectors • Impractical for large n ( > 20 )

Random Pattern Testing Bottom: Random- Pattern Resistant circuit

Pseudo-Random Pattern Generation • StandardLinear Feedback Shift Register (LFSR) • Normally known as External XOR type LFSR • Produces patterns algorithmically – repeatable • Has most of desirable random # properties • Need not cover all 2n input combinations • Long sequences needed for good fault coverage

Test Pattern Augmentation • Secondary ROM – to get LFSR to 100% SAF coverage • Add a small ROM with missing test patterns • Add extra circuit mode to Input MUX – shift to ROM patterns after LFSR done • Important to compact extra test patterns • Use diffracter: • Generates cluster of patterns in neighborhood of stored ROM pattern • Transform LFSR patterns into new vector set • Put LFSR and transformation hardware in full-scan chain

Response Compaction • Severe amounts of data in CUT response to LFSR patterns – example: • Generate 5 million random patterns • CUT has 200 outputs • Leads to: 5 million x 200 = 1 billion bits response • Not economical to store and check all of these responses on chip • Responses must be compacted

Definitions • Aliasing – Due to information loss, signatures of good and some bad machines match • Compaction – Drastically reduce # bits in original circuit response – lose information • Compression – Reduce # bits in original circuit response – no information loss – fully invertible (can get back original response) • Signature analysis – Compact good machine response into good machine signature. Actual signature generated during testing, and compared with good machine signature

LFSR for Response Compaction • Use cyclic redundancy check code (CRCC) generator (LFSR) for response compacter • Treat data bits from circuit POs to be compacted as a decreasing order coefficient polynomial • CRCC divides the PO polynomial by its characteristic polynomial • Leaves remainder of division in LFSR • Must initialize LFSR to seed value (usually 0) before testing • After testing – compare signature in LFSR to known good machine signature • Critical: Must compute good machine signature

Example Modular LFSR Response Compacter • LFSR seed value is “00000”

Summary • LFSR pattern generator and MISR response compacter – preferred BIST methods • BIST has overheads: test controller, extra circuit delay, Input MUX, pattern generator, response compacter, DFT to initialize circuit & test the test hardware • BIST benefits: • At-speed testing for delay & stuck-at faults • Drastic ATE cost reduction • Field test capability • Faster diagnosis during system test • Less effort to design testing process • Shorter test application times

Overview: Boundary Scan • Motivation • System view of boundary scan hardware • Elementary scan cell • Test Access Port (TAP) controller • Boundary scan instructions • Summary

Motivation for Standard • Bed-of-nails printed circuit board tester gone • We put components on both sides of PCB & replaced DIPs with flat packs to reduce inductance • Nails would hit components • Reduced spacing between PCB wires • Nails would short the wires • PCB Tester must be replaced with built-in test delivery system -- JTAG does that • Need standard System Test Port and Bus • Integrate components from different vendors • Test bus identical for various components • One chip has test hardware for other chips

System Test Logic

System View of Interconnect

ECE 551: Digital System Design & Synthesis