MSP430

1. MSP430 Signal Acquisition & DAC operations using MSP430

2. Sampling Sampling refers to the process of converting a continuous, analog signal to discrete digital numbers. Typically, an Analog to Digital Converter (ADC) would be used to convert voltages to a digital number corresponding to a certain voltage level.

3. Resolution The number of bits used to represent a sampled, analog signal is known as the resolution of the converter. This number is also related to the total number of unique digital values that can be used to represent a signal. For example, if a given ADC has a resolution of 12 bits, then it can represent 4,096 discrete values, since 2^12 = 4,096; if the resolution is 16 bits, it can represent 65,536 discrete values. We may also think about resolution from an electrical standpoint, which is expressed in volts. In that case, the resolution the ADC is equal to the entire range of possible voltage measurements divided by the number of quantization levels. Voltage levels that fall outside the ADC’s possible measurement range will saturate the ADC. They will be sampled at the highest or lowest possible level the ADC can represent.

4. Resolution • For example, ADC specifications could be as follows: • Full scale measurement range: -5 to 5 volts • ADC resolution 12 bits: 2^12=4,096  quantization levels • ADC voltage resolution is: 5V−-5V/4096=0.0024 V=2.4 mV Large ranges of voltages will fall into in a single quantization level, so it is beneficial to increase the resolution of the ADC in order to make the levels smaller. The accuracy of an ADC is strongly correlated with its resolution however; it is ultimately determined by the Signal to Noise Ratio (SNR) of the signal. If the noise is much greater relative to the strength in the signal, then it doesn't really matter how good or bad the ADC is. In general, adding 1 more bit of resolution is equal to a 6 dB gain in SNR.

5. Sampling Rate Analog signals are continuous in time. In order to convert them into their digital representation we must sampled them at discrete intervals in time. The interval at which the signal is captured is known as the sampling rate of the converter. If the sampling rate is fast enough, then the stored, sampled data points may be used to reconstruct the original signal exactly from the discrete data by interpolating the data points. Ultimately, the accuracy of the reconstructed signal is limited by the quantization error, and is only possible if the sampling rate is higher than twice the highest frequency of the signal. This is the basis for the Shannon-Nyquist Sampling Theorem.

6. Analog-to-Digital Converter on the MSP430 • The analog to digital converter (ADC) on the MSP430F169 is a 12 channel, 12 bit converter. The module is highly configurable and can run largely free of program involvement. In this portion of the lab, we will broadly explain the features of the module, but the particular effects of each register are listed, as usual, in the User’s Guide.

7. Range of Measurement • The result of each conversion will be 12 bits long in the form of an unsigned integer whose value is: 4095x (Vin – Vrneg)/ (Vrpos – Vrneg) where Vin is the input voltage to be measured, Vrneg is the lower reference voltage, and Vrpos is the higher reference voltage. The reference voltages are set to power and ground by default (3.3V and 0V), but they can be changed to several other possibilities using the ADC12 Conversion Memory Control Registers (ADC12MCTLx). This allows each sample to choose its own voltage references. This register also allows for selection of the input channel for each sample. The highest bit of the register is used for multi-channel sequences. This EOS bit indicates the last sample of a sequence

8. Operation Modes of the ADC • The ADC12 has four basic operation modes: • Single channel, single conversion This mode corresponds to a request by the processor for a single sample from a single channel. Interrupts can still be used to indicate when the conversion is complete. The ADC will write the conversion to the ADC12MEMx cell indicated by the CSTARTADDx bits. • Single channel, repeated conversions This mode uses a single ADC12MEMx cell as indicated by the the CSTARTADDx bits. Because this mode only uses a single memory cell, the results must be collected after each conversion. The interrupt flag is set after each conversion. • Multiple channels, single conversion each A sequence is set up using the ADC12MCTLx registers to configure each memory slot to sample with the desired parameter. Each cell will take one sample before the sequence will need to be reinitiated. An interrupt flag will be set after each conversion. • Multiple channels, repeated conversions A sequence is set up using the ADC12MCTLx registers to configure each memory slot to sample in the desired way. The sequence will repeat with the interrupt flag being set after each sample.

9. A/D Example //******************************************************************************// MSP430xG461x Demo - ADC12, Using the Internal Reference//// This example shows how to use the internal reference of the ADC12.// It uses the internal 2.5V reference and performs a single conversion// on channel A0. The conversion results are stored in ADC12MEM0. Test by// applying a voltage to channel A0, then setting and running to a breakpoint// at "__no_operation()".// To view the conversion results, open a register window in Debugger and// view the contents of ADC12MEM0.// ACLK = 32kHz, MCLK = SMCLK = default DCO 1048576Hz, ADC12CLK = ADC12OSC//// MSP430xG461x// ---------------// | XIN|-// | | 32kHz// Vin -->|P6.0/A0 XOUT|-// | |// A. Dannenberg/ M. Mitchell// Texas Instruments Inc.// October 2006// Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.41A//******************************************************************************#include "msp430xG46x.h"volatile unsigned int i;void main(void){WDTCTL = WDTPW + WDTHOLD; // Stop watchdogP6SEL |= 0x01; // Enable A/D channel A0ADC12CTL0 = REFON + REF2_5V + ADC12ON + SHT0_2;// turn on 2.5V ref, set samplng timeADC12CTL1 = SHP; // Use sampling timerADC12MCTL0 = SREF_1; // Vr+=Vref+for (i = 0x3600; i; i--); // Delay for needed ref start-up.// See datasheet for details.ADC12CTL0 |= ENC; // Enable conversionswhile (1){ADC12CTL0 |= ADC12SC; // Start conversionswhile (!(ADC12IFG & 0x0001)); // Conversion done?ADC12MEM0; // Access result__no_operation(); // SET BREAKPOINT HERE}}

10. DAC: Lab1 - Voltage ramp generator This laboratory gives an example of the use of the DAC available in the MSP-EXP430FG4618 Development Tool. The DAC module reference is obtained from the ADC module. The DAC is configured with 12 bits resolution in straight binary format. The DAC’s output value is updated every 1 msec by a Timer_A ISR. The buttons SW1 and SW2 are used to manually modify the DAC’s output. This laboratory ( Lab1_DAC.c )implements a voltage ramp generator. The DAC module reference is obtained from the ADC module. The DAC is configured with 12-bit resolution, in straight binary format. The output of the DAC value is updated once every 1 msec by an interrupt service routine (ISR) generated by Timer_A. The push buttons SW1 and SW2 are used to manually modify the output of the DAC value. When the microcontroller is not performing any task, it enters low power mode.

11. Resources The DAC12_0 module uses VREF+ as reference voltage. It is therefore necessary to activate this reference voltage in the ADC12 module. The DAC12_0 is connected to Port P6.6 on the Header 8 pin 7. Connect the oscilloscope probe to this port pin. The output of the DAC is updated whenever Timer_A generates an interrupt. This peripheral is configured to generate an interrupt with a 1 msec time period. After refreshing the output of the DAC, the system returns to low power mode LPM3. The push buttons SW1 and SW2 allow the output of the DAC value to be changed manually. The resources used by the application are: - Timer_A; - DAC12; - I/O ports; - FLL+; - Interrupts.

12. Software application organization The application starts by stopping the Watchdog Timer. Then, the ADC12’s reference voltage is activated and set to 2.5 V. A delay is used to allow the reference voltage to settle. During this time period, the device enters low power mode LPM0. The delay period, which is controlled by Timer_A, enables an interrupt when it completes. The interrupt wakes the device and proceeds with the execution of the application. Timer_A is reconfigured to generate an interrupt once every 1 msec. This interrupt service routine (ISR) updates the output of the DAC. Ports P1.0 and P1.1 are connected to buttons SW1 and SW2. The ports are configured as inputs with interrupt capability, such that the ISR can decode which button is pushed. If the interrupt source is due to button SW1, then the output of the DAC is increased. If the interrupt source is due to button SW2, then the output of the DAC is decreased.

13. System configuration • Reference voltage selection The DAC12_0 uses the signal VREF+ as reference voltage. What is the value to write to the configuration register in order to obtain the internally available reference? ADC12CTL0 = REF2_5V | REFON; // Internal 2.5V ref on

14. DAC12 configuration The DAC12_0 is configured with 12-bit resolution. The output is updated immediately when a new DAC12 data value is written in straight binary data format to the DAC12_0DAT register. The full-scale output must be equal to the VREF+ 2.5 V internal reference voltage. Choose a compromise solution between the settling time and current consumption, by selecting a medium frequency and current for both input and output buffers. Configure the following register in order to meet these specifications: DAC12_0DAT = 0x00; // DAC_0 output 0V DAC12_0CTL = DAC12IR | DAC12AMP_5 | DAC12ENC; // DAC_0 -> P6.6, // DAC_1 -> P6.7, // DAC reference Vref, // 12 bits resolution, // Immediate load, // DAC full scale output, // Medium speed/current, // Straight binary, // Not grouped

15. Timer_A configuration • Configure Timer_A register to enable an interrupt once every 1 msec. Use the ACLK clock signal as the clock source. This timer is configured in count up mode in order to count until the TAR value reaches the TACCR0 value. // Before entering in LPM0: TACTL = TACLR | MC_1 | TASSEL_2; // up mode, SMCLK // Timer_A ISR: TAR = 0; // TAR reset TACCR0 = 13600; // Delay to allow Ref to settle TACCTL0 |= CCIE; // Compare-mode interrupt TACTL = TACLR | MC_1 | TASSEL_2; // up mode, SMCLK //********************************************************* // ISR to TACCRO from Timer A //********************************************************* #pragma vector=TIMERA0_VECTOR __interrupt void TimerA0_ISR (void) { DAC12_0DAT++; // Increase DAC's output if (DAC12_0DAT == 0xfff) DAC12_0DAT = 0; // reset DAC's output if (flag == 1) // if flag active exite LPM0 { flag = 0; LPM0_EXIT; } }

16. I/O Ports configuration • Port P1 uses the bits P1.0 and P1.2 to activate the ISR whenever the push buttons SW1 and SW2 are activated (low-to-high transition). // SW1 and SW2 ports configuration P1SEL &= ~0x03; // P1.0 and P1.1 I/O ports P1DIR &= ~0x03; // P1.0 and P1.1 digital inputs P1IFG = 0x00; // clear all interrupts pending P1IE |= 0x03; // enable port interrupts // DAC12_0 is connected to P6.6. Configure P6 as a special function output:

17. // P6.6 (DAC12_0 output) • // There is no need to configure P6.6 as a • // special function output since it was configured in the • // DAC12 configuration register (DAC12_0CTL) using • // DAC12OPS = 0 //*********************************************** // Port1 Interrupt Service Rotine //************************************************ #pragma vector=PORT1_VECTOR • __interrupt void PORT1_ISR (void) • { • if (P1IFG & 0x01) // SW1 generate interrupt • DAC12_0DAT += 400; // DAC's output increases • if (P1IFG & 0x02) // SW2 generate interrupt • DAC12_0DAT -= 400; // DAC's output decreases • P1IFG = 0x00; // clean all pending interrupts • }

18. Analysis of operation • Observe the analogue signal using an oscilloscope After compiling the project and starting the debug session, monitor the operation of the application using an oscilloscope probe connected to pin 7 of Header 8 (P6.6).