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Chapter 2

Chapter 2. Logic Gates By Taweesak Reungpeerakul. Contents. Inverter AND Gate OR Gate NAND Gate NOR Gate XOR and XNOR Gates Integrated Circuit Logic Gates. Symbols Truth Table In Out 0 1 1 0. Timing Diagram Logic Expression: Out = In. 2.1 Inverter (INV). 0. 1. 1.

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Chapter 2

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  1. Chapter 2 Logic Gates By Taweesak Reungpeerakul

  2. Contents • Inverter • AND Gate • OR Gate • NAND Gate • NOR Gate • XOR and XNOR Gates • Integrated Circuit Logic Gates 242-208 CH2

  3. Symbols Truth Table In Out 0 1 1 0 Timing Diagram Logic Expression: Out = In 2.1 Inverter (INV) 0 1 1 0 242-208 CH2

  4. Symbols Truth Table A B Out 0 0 0 0 1 0 1 0 0 1 1 1 Timing Diagram Logic Expression: Out = AB 2.2 AND Gate 242-208 CH2

  5. Symbols Truth Table A B Out 0 0 0 0 1 1 1 0 1 1 1 1 Timing Diagram Logic Expression: Out = A+B 2.3 OR Gate 242-208 CH2

  6. Symbols Truth Table A B Out 0 0 1 0 1 1 1 0 1 1 1 0 Timing Diagram Logic Expression: Out = AB 2.4 NAND Gate 242-208 CH2

  7. Symbols Truth Table A B Out 0 0 1 0 1 0 1 0 0 1 1 0 Timing Diagram Logic Expression: Out = A+B 2.5 NOR Gate 242-208 CH2

  8. Symbols Truth Table A B Out 0 0 0 0 1 1 1 0 1 1 1 0 Timing Diagram Logic Expression: Out = AB+AB; AB 2.6 XOR Gate 242-208 CH2

  9. Symbols Truth Table A B Out 0 0 1 0 1 0 1 0 0 1 1 1 Timing Diagram Logic Expression: Out = AB+AB; AB XNOR Gate 242-208 CH2

  10. CMOS: Complementary Metal-Oxide Semiconductor Low Power Dissipation DC Power Supply: 5 V & 3.3 V CMOS Series: 74 + letter(s) + numbers Letters: HC, HCT = High-speed CMOS LV, LVC = Low-voltage CMOS BCT = BiCMOS (combine CMOS&TTL) Numbers: 00= Quad 2-input NAND 02= Quad 2-input NOR 04= Hex inverter TTL: Transistor-Transistor Logic Not Sensitive to Electrostatic Discharge Switching Speed DC Power Supply: 5 V TTL Series: 74 + letter(s) + numbers Letters: S = Schottky TTL LS = Low-power Schottky TTL F = Fast TTL Numbers: 08= Quad 2-input AND 10= Triple 3-input NAND 32= Quad 2-input OR 2.7 Integrated Circuit Logic Gates 242-208 CH2

  11. Packages DIP IC Gate Config. 2.7 IC Logic Gate (cont.) 242-208 CH2

  12. Propagation Delay Time: tP , tPHL , tPLH DC Power Supply: 3.3, 5V Power Dissipation (PD) PD = VCC (ICCH+ICCL)/2 I/O Logic Levels TTL: VIL =0.8 V, VIH =2 V VOL =0.4 V, VOH =2.4V Speed-power Product (SPP) SPP = tP*PD Fan-out and Loading Fan-out: max # gates connected at the output pin Unit loads = IOH/IIH or IOL/IIL Data Sheets Performance Characteristics & Parameters 242-208 CH2

  13. Contents (Session 2) • Boolean Operations & Expressions • Rules of Boolean Algebra • DeMorgan’s Theorems • Simplification Using Boolean Algebra • Standard Forms of Boolean Algebra • Karnaugh Map 242-208 CH2

  14. Boolean Addition is equivalent to the OR operation. 0+0 = 0 0+1 = 1 1+0 = 1 1+1 = 1 Boolean multiplication is equivalent to the AND operation. 0·0 = 0 0·1 = 0 1·0 = 0 1·1 = 1 2.8 Boolean Operations & Expressions 242-208 CH2

  15. A+B = B+A AB = BA A+ (B+C) = (A+B)+C A(BC) = (AB)C A(B+C) = AB+AC A+0=A A·A=A A+1=1 A·A=0 A·0=0 A=A A·1=A A+A=A A+A=1 A+AB=A A+AB=A+B (A+B)(A+C)=A+BC 2.9 Rules of Boolean Algebra 242-208 CH2

  16. 2.10 DeMorgan’s Theorems • The complement of a product of variables is equal to the sum of the complements of the variables. XY = X + Y • The complement of a sum of variables is equal to the product of complements of the variables. X + Y = X·Y 242-208 CH2

  17. Ex#1: (AB+C)(BC) = (AB+C) +(BC) = (AB)C +(B+C) = (A+B)C + B+C Question: (A+B)CD Ans: (A ·B)+C+D Ex# 2: AB + CDE = (AB) · (CDE) = (A+B) · (CD+E) = (A+B) · (CD+E) Question: A+B+C+DE Ans: ABC+D+E Examples of DeMorgan’s theorem 242-208 CH2

  18. 2.11 Boolean Analysis of Logic Circuits Truth Table A B C D (AB+C)D 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 A AB B AB+C C D (AB+C)D 242-208 CH2

  19. EX#1: AB+A(B+C)+B(B+C) = AB+AB+AC+BB+BC = AB + AC + B + BC = B + AC Question: AB+AC+ABC Ans: A+BC EX#2: ABC+ABC+ABC+ABC+ABC = BC+ABC+ABC+ABC = BC+BC+ABC = BC+B(C+AC) = BC+B(C+A) = BC+BC+AB 2.12 Simplification using Boolean Algebra 242-208 CH2

  20. Sum-of-Products (SOP): 2 or more product terms are summed by Boolean addition such as AB+ABC+AC Ex# 1: (A+B)(C+D)  SOP form = AC+AD+BC+BD Ex# 2: (A + B) + C = AC + BC Standard SOP Form: all variables in the domain appear in each product term such as ABC+ABC+ABC Ex# 1: AB+ABC  standard SOP = AB(C+C)+ABC = ABC+ABC+ABC Ex# 2: B+ABC = B(A+A)+ABC = AB+AB+ABC = AB(C+C)+AB(C+C)+ABC = ABC+ABC+ABC+ABC+ABC 2.13 Standard Forms of Boolean Expressions 242-208 CH2

  21. Product-of-Sum (POS): 2 or more sum terms are multiplied such as (A+B)(A+B+C) Standard POS: all variables in the domain appear in each sum term such as (A+B+C)(A+B+C) Ex# 1: (A+C)(A+B+C)  standard POS = (A+C+BB)(A+B+C) =(A+B+C) (A+B+C) (A+B+C) Question: (A+C)(A+B)  std. POS Standard Forms (cont.) Ans: (A+B+C) (A+B+C) (A+B+C)(A+B+C) 242-208 CH2

  22. Std. SOP to std. POS Example: ABC+ABC+ABC+ABC+ABC 101 011 100 001 000 3 variables 23 = 8 possible combinations Remained terms: 111, 110, 010 Std. POS = (A+B+C)(A+B+C)(A+B+C) 242-208 CH2

  23. SOP  Truth Table EX: ABC+ABC+ABC+ABC 000 010 101 110 out=1 A B C Out 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0 POS Truth Table EX: (A+B+C)(A+B+C)(A+B+C) 100 010 011 out=0 A B C Out 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 2.14 Boolean Expressions and Truth Tables 242-208 CH2

  24. 2.15 The Karnaugh Map • The Karnaugh map is an array of cells in which each cell represents a binary value of the input variables. • The number of cells is 2n, n is number of variables 3 Variables ABC ABC ABC ABC ABC ABC ABC ABC Question: 4 variables Karnaugh map 242-208 CH2

  25. 2.16 Karnaugh Map SOP Minimization Ex1: Map and minimize the following std. SOP expression on a Karnaugh map: ABC+ABC+ABC+ABC 000 001 110 100 AB 1 1 1 1 1 1 1 1 AC Answer: AB+AC 242-208 CH2

  26. SOP Minimization (cont.) Ex2: Map and minimize the following SOP expression on a Karnaugh map: AB+ABC+ABC 110 111 010 011 B 1 1 1 1 1 1 1 1 Answer: B 242-208 CH2

  27. Karnaugh Map Simplification • Grouping 1s - Each group must contain 1,2,4,8,or 16 - Each cell in a group must be adjacent to one or more cells in that same group, but all cells in the group do not have to be adjacent to each other. - Always include the largest possible number of 1s in a group - Each 1 on the map must be included in at least one group. The 1s already in a group can be included in another group as long as the overlapping groups include non-common 1s. 242-208 CH2

  28. Group the 1s in each of the Karnaugh maps ABC AC BC D BC ABC 1 1 1 1 1 1 1 1 1 AB C AB 1 1 1 1 1 1 1 1 1 1 1 1 242-208 CH2

  29. 2.17 Karnaugh Map POS Minimization Ex1: Map and minimize the following std. POS expression on a Karnaugh map: (A+B+C)(A+B+C)(A+B+C)(A+B+C) 000 001 111 110 A+B 0 0 0 0 0 0 0 0 A+B Answer: (A+B)(A+B) 242-208 CH2

  30. POS Minimization (cont.) Ex2: Map and minimize the following POS expression on a Karnaugh map: (A+B)(A+B+C)(A+B+C) 000 001 010 011 A 0 0 0 0 0 0 0 0 Answer: A 242-208 CH2

  31. Karnaugh maps Simplification of POS Expressions (B+C+D)(A+C+D)(A+B+C+D)(A+B+C+D)(A+B+C+D) 0000 1000 0010 0110 1011 1001 1010 (B+D) (A+C+D) 0 0 0 (A+B) 0 0 0 0 Answer: (B+D)(A+B)(A+C+D) 242-208 CH2

  32. Converting Between POS and SOP Using Karnaugh Map (B+C+D)(A+C+D)(A+B+C+D)(A+B+C+D)(A+B+C+D) 0000 1000 0010 0110 1011 1001 1010 (B+D) AD BC (A+C+D) 0 0 0 1 1 0 0 0 1 1 1 AB (A+B) 1 1 1 1 0 0 0 0 0 0 0 0 Min POS: (B+D)(A+B)(A+C+D) Min SOP: AB+BC+AD 242-208 CH2

  33. Mapping Directly from a Truth Table A B C Out 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 x 1 1 x 1 Out = AB+BC 242-208 CH2

  34. 7-segment decoding Logic Digit D C B A a b c d e f g 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0 2 0 0 1 0 1 1 0 1 1 0 1 3 0 0 1 1 1 1 1 1 0 0 1 4 0 1 0 0 0 1 1 0 0 1 1 5 0 1 0 1 1 0 1 1 0 1 1 6 0 1 1 0 1 0 1 1 1 1 1 7 0 1 1 1 1 1 1 0 0 0 0 8 1 0 0 0 1 1 1 1 1 1 1 9 1 0 0 1 1 1 1 1 0 1 1 10 1 0 1 0 x x x x x x x 11 1 0 1 1 x x x x x x x 12 1 1 0 0 x x x x x x x 13 1 1 0 1 x x x x x x x 14 1 1 1 0 x x x x x x x 15 1 1 1 1 x x x x x x x 242-208 CH2

  35. Karnaugh Map Minimization of the Segment Logic SOP for segment a: DC BA+DCBA+DCBA+ DCBA+DCBA+DCBA+DC BA+DCBA CA 1 1 1 CA B 1 1 1 D x x x x 1 x 1 x Minimum SOP expression: D+B+CA+CA 242-208 CH2

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