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EET 450

EET 450 . Chapter 2 – How hardware and Software Work Together. The BOOT process. CPU executes instructions sequentially. On power on – a power-on-reset is usually invoked. Program execution begins from a predetermined memory location (FFFF0h)

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EET 450

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  1. EET 450 Chapter 2 – How hardware and Software Work Together

  2. The BOOT process • CPU executes instructions sequentially. On power on – a power-on-reset is usually invoked. • Program execution begins from a predetermined memory location (FFFF0h) • This location typically contains only an unconditional jump – to the beginning of BIOS boot routine • BIOS – Basic Input Output System

  3. The BOOT process • BIOS leads the computer through the boot process • Cold Boot • Power On Self Test (POST) • Verify boot settings in CMOS • Load Master Boot Record (MBR) from boot device • MBR contains location of OS boot routine (usually) • Warm Boot • Skips POST

  4. The BOOT process • The BIOS load routine resolves resource assignments – either statically or dynamically • PNP devices allow automatic assignment • IRQ – Interrupt Request Vectors • I/O Addresses – physical address of I/O device/port

  5. The BOOT process • Memory Addresses – portions of memory space assigned to ROM • DMA Channel – Direct Memory Access channel

  6. OS Load • MBR directs CPU to routine that will complete loading the operating system • An I/O module containing device drivers and parameters for operating installed physical resources is loaded (IO.SYS) • A User Interface is loaded to display information to user and allow keyboard/mouse input

  7. OS Load • Initial (setup) programs are executed. • Memory resident programs are loaded into memory with appropriate resource redirection.

  8. Interrupts • IRQ – Interrupt Request Number • Provides direction to interrupt vector – location of Interrupt Service Routine (ISR)

  9. Memory Addresses • Memory Addressing • Segmented Memory • REAL mode memory addressing • Memory Map

  10. Input/Output Addressing • The CPU provides separate methods & instructions for addressing memory and I/O • Table 2-6 contains normal IRQ and Addressing assignments

  11. Assignment • Read Chapter 3 • Start research on Motherboards/Chipsets • Review LINKS

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