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Computer Architecture The Anatomy of Modern Processors

Computer Architecture The Anatomy of Modern Processors. Cores, Peripheral Devices, Embedded Processors and other useful things … John Morris. Architectures, Implementations and Systems. Intel defined an architecture Then they built a processor to execute it - the 8088

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Computer Architecture The Anatomy of Modern Processors

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  1. Computer ArchitectureThe Anatomy of Modern Processors Cores, Peripheral Devices, Embedded Processors and other useful things … John Morris

  2. Architectures, Implementations and Systems • Intel defined an architecture • Then they built a processor to execute it - the 8088 • Then they built a family of processors executing the 8088 architecture: • 8086, 80188, 80186, 80286, 80386, all Pentiums • Other manufacturers have also built processors that will run the same instructions • AMD, … • These were built into systems,eg the original IBM PC • 8088 chip, memory (all 64kb!), floppy disc, etc Implementations Anatomy of Modern Processors

  3. Architectures, Implementations and Systems • An extension of the 8088 architecture, generally referred to as x86, was then defined • Then they built a family of processors executing the x86 architecture: • 8086, 80186, 80286, 80386, all Pentiums • Other manufacturers have also built processors that will run the same instructions • AMD, … • IBM built the ‘AT’ PCs - systems incorporating x86 processors Implementations Anatomy of Modern Processors

  4. Architectures, Implementations and Systems • An extension of the 8088 architecture, generally referred to as x86, was then defined • Then they built a family of processors executing the x86 architecture: • 8086, 80186, 80286, 80386, all Pentiums • Other manufacturers have also built processors that will run the same instructions • AMD, … • IBM built the ‘AT’ PCs - systems incorporating x86 processors Implementations Anatomy of Modern Processors

  5. Architectures, Implementations and Systems • When the x86 became too small to cope with Microsoft induced code bloat, the Pentium architecture was defined • and a family of processors executing the Pentium architecture built: • Pentium, Pentium II, III, … , Celeron, Xeon, … • Other manufacturers have also built processors that will run the same instructions • AMD, … • A modern PC is a systems incorporating one (or more) Pentium architecture processors Implementations Anatomy of Modern Processors

  6. Architectures, Implementations and Systems • Similarly Motorola defined the 68000 architecture and built a processor to implement it • Then a family of processors executing the 68xxx architecture were built: • 68010, 68020, 68030, 68040 • Original Macintosh systems used 68xxx processors • When Apple migrated to the IBM/Motorola Power architecture • PowerPC based systems executed 68xxx instructions by emulation in software • So you could almost say that PowerPCs were 68xxx architecture machines too! • To solve the backward compatibility requirement • Apple’s alternative could have built a microcoded processor which executed 68xxx instructions in microcode Implementations Anatomy of Modern Processors

  7. Architectures, Implementations and Systems • Many other families of processors having the same architecture (executing the same basic instruction set) exist • IBM’s 360 series • Many microcoded • IBM’s 370 series • IBM/Motorola PowerPC • Started with a multi-chip implementation • Original ‘Power’ architecture • As technology improved, they could fit it all on one chip • PowerPC architecture • And • A Series of processors implementing it Anatomy of Modern Processors

  8. Peripheral Devices • A CPU isn’t much good if all it can do is calculate! • Particularly if it needs to interact with some environment • eg control or monitor some device(s) How does a CPU interact with peripheral devices? • Two strategies • Specific input/output (I/O) instructions • x86 architecture includes • in register, port • out port, register • address was limited to 20(?) bits • register was AL or AX • Remember x86 has designated-purpose registers! • Separate memory and I/O address spaces • ie address fc0016 can be a device or a memory address • x86 buses have a MEMSEL line which selects the address space Anatomy of Modern Processors

  9. Peripheral Devices How does a CPU interact with peripheral devices? • Two strategies • Specific input/output (I/O) instructions • Separate memory and I/O address spaces • ie address fc0016 can be a device or a memory address • x86 buses have a MEMSEL line which selects the address space • Devices are memory-mapped • An area of memory is reserved for devices • Devices are seen by the processor as memory st r4, r3 ;Store value in r4 at the address in r3 ;r3 contains the address of some peripheral ld r4,(4)r3 ;Read a word into r4 from (r3)+4 ;Read from the second word in a block of ;memory allocated to a peripheral Anatomy of Modern Processors

  10. Addressing Devices Model 1Separate address spaces Model 2Memory-mapped devices ffffffff ffffffff Device B ffffd000 Device A fffff ffffc000 Device B fd000 Device A fc000 Instruction and Data Memory 0 I/O AddressSpace 0 Memory Address Space 0 Anatomy of Modern Processors

  11. Designing an I/O interface Control lines* Device Interface CPU Address Recognition Device Select Enable DeviceLogic Address bus Data bus * Include MEMSELfor an x86 Anatomy of Modern Processors

  12. Device Interface • Bus transaction • Operation • CPU requests bus • CPU asserts command, address • Device recognises address • Asserts internal Device Select line • Device logic completes data phases Anatomy of Modern Processors

  13. Programming a Device • Device specification will normally include • Instructions for setting the address to which the device will respond • Sometimes these are fixed eg MS-DOS fixes addresses at which printer, serial lines, etc should be placed Printer at 3F8 Serial line at xxx (?) • Choose a suitable address range for the device • It musn’t conflict with another device! • Descriptions of registers in the device’s address space • Configuration • Control • Data • Status Anatomy of Modern Processors

  14. Programming a Device • Writing a device driver • Device drivers will normally have these steps • Configure the device • Write configuration patterns to configuration register(s) • Set basic capabilities and performance • Input or output • Speed • eg Baud rate for a serial line • Write commands to command registers • For example • Read / write • Select sub-device • eg Multiple discs on one controller • Disc block address • Read from / Write to data registers Anatomy of Modern Processors

  15. Programming a Device • Handling slow devices • Almost all real devices are slow (relative to the CPU!) • Data may not be available immediately (on a read) • or • Device may not be ready to take data (on a write) • Device can’t take new data until old data has been despatched / written / settled / … • Device drivers deal with this in two ways • Read a status register • Status register has a ready bit • Poll the register until it’s set • Uses a program loop • Simple, but inefficient • OK when • Delay is short • There’s nothing else the CPU can do • Simple code (engineering time) is more important! • Hardware doesn’t provide / support interrupts • Write an interrupt handler • … Anatomy of Modern Processors

  16. Interrupts • Processors will normally support interrupts • One or more pins accept signals which interrupt normal sequential processing of instructions • Immediate jump to an interrupt handler • Typical system will provide for several interrupt handlers • Efficient support for multiple devices • If there is only one interrupt handler,it will need to check status registers for all the devicesto determine which one interrupted this time • Significant software overhead • Significant maintenance overhead • Main Interrupt handler has to be changed every time a new device is added • Example:Intel x86 support for multiple devices • An area in low memory reserved for addresses of interrupt handlers • When a device interrupts, it also sends its interrupt number to the CPU • Interrupt number is an index into the interrupt table • Actual address of an interrupt handler Anatomy of Modern Processors

  17. x86 Interrupt Table Handler for device 1 20200 Handler for device 0 Address of Handler for device nis found at address 4*n 200fc 12 • Processor reads interrupt number from bus, • fetches interrupt handler address from 4*n • and • jumps to handler 8 20200 4 200fc 0 Anatomy of Modern Processors

  18. Device Control from HLL • Separate address space architectures • OS needs to provide two functions • int in( port ); • void out( port, value ); • A safe OS needs to ensure that these functions can only access certain devices! • If there is a device at port fc0016then • x = in ( 0xfc00 ) • reads from one register of the device • and • out( 0xfc04, 100 ) • writes to an output register on the same device Anatomy of Modern Processors

  19. Device Control from HLL • Memory mapped architectures • In C, the ability to assign a value to a pointermakes accessing devices easy: • #define base_address 0xfc00 • int *base_pt = base_address; • /* Write to the device */ • *base_pt = value; • /* Read from the device */ • x = *(base_pt+1); • A safe OS needs to ensure that only certain processes can access these addresses! • Protection usually handled by a Memory Mapping Unit (MMU) • Translates virtual addresses emitted by a program to physical addresses and verifies access rights • (More in SOFTENG 363) Anatomy of Modern Processors

  20. Device Control from HLL • Memory mapped architectures • In Java, safe typing makes the sort of code that is ‘normal’ in C difficult to write! • Need to resort to Java Native Interface (JNI) • Java interface to C (or other HLLs) • Specific to a target architecture! Anatomy of Modern Processors

  21. Device Control from HLL • Typical device • Several ‘registers’ for • configuration, • status, • command, • data • Located at offsets from some base address • eg • base+0 configuration register • base+2 status register • base+4 command register • base+6 data register • Addresses separatedby 2 bytes • 16-bit device with • 16-bit registers! Anatomy of Modern Processors

  22. Thresholdvalue Alarms Interruptenable 15-8 7-1 0 Device Control from HLL • Documentation will give formats for words written to or read from these ports • eg Configuration register • bit 0 - set to enable interrupts • bits 1-7 - set to enable threshhold alarms from ports 1-7 • bits 15-8 - 8-bit value of threshold Anatomy of Modern Processors

  23. Not used Ready Interruptenabled 15-2 1 0 Device Control from HLL • Documentation will give formats for words written to or read from these ports • eg Status register • bit 0 - set when interrupts are enabled • bits 1 - set when the device is not busy • bits 15-2 - not used Anatomy of Modern Processors

  24. Thresholdvalue Alarms Interruptenable 15-8 7-1 0 Device Control from HLL Configuration register • To set the configuration register • #define BASE_ADDRESS 0xfc00#define INT_ENABLE 1#define AL_ON 1 • unsigned short *base_pt = BASE_ADDRESS;unsigned short config = INT_ENABLE | (AL_ON<<1) | (AL_ON<<4) | (25<<8) • *base_pt = config; Constant for base address Constants for sections of the configuration word Form a configuration command by or’ing together the required bits - Shifting patterns as needed Write the configuration wordto the configuration register Anatomy of Modern Processors

  25. Device Control from HLL • Memory mapped architectures • Since there will generally be a group of registers for any device,in C, you can use C struct’s to produce ‘elegant’ code! • A struct is the forerunner of today’s objects • It enables related data items to be encapsulated in one logical structure, eg • struct point3D { float x, y, z; } • encapsulates 3 floats into a structure which models a point in 3D space • In Java, you would make a class: • class point3D { float x, y, z; • … // Some methods for operating on the … // attributes • } Anatomy of Modern Processors

  26. In all cases, qualify the typeasunsigned Device Control from HLL • Memory mapped architectures • For the device, you define a struct whose ‘elements’ are the registers used to control the device • struct deviceX { • unsigned short config, status, • command, • data }; • The elements of the struct are laid out in memory in the same order as the device’s registers. • Choose data types to correspond to the register width • For 8-bit registers, use char • For 16-bit registers, use short • For 32-bit registers, use int • In all cases, qualify the type asunsigned This prevents the compiler from generating arithmeticinstructions that extend the sign - In this case, you want tomanipulate bit patterns! Warning This will usually work,but C has some arcane rules which you should learn about before doing this! Anatomy of Modern Processors

  27. Device Control from HLL • Memory mapped architectures • struct deviceX { • unsigned short config, status, • command, • data }; • Declare a pointer to the struct and initialize it to point to the device’s base address: • struct deviceX *x = BASE_ADDRESS; • Now you can refer to the registers in a natural way: • x->config = INT_ENABLE|(AL_ON<<1)|(AL_ON<<4)|(25<<8); • stat = x->status; /* Read status */ • if ( stat & READY ) { x->command = READ; • ... Anatomy of Modern Processors

  28. READY is bit 1 in the status register In C, any non-zero value isconsidered TRUE, so if a bit is set anywhere in a word, you just use & with a mask The mask contains the bit(s) that should be set Device Control from HLL • Memory mapped architectures • struct deviceX { • unsigned short config, status, • command, • data }; • struct deviceX *x = BASE_ADDRESS; • x->config = INT_ENABLE|(AL_ON<<1)|(AL_ON<<4)|(25<<8); • stat = x->status; /* Read status */ • #define READY 0x2 • if ( stat & READY ) { x->command = READ; • ... Anatomy of Modern Processors

  29. Device Control from HLL • Memory mapped architectures • struct deviceX { • unsigned short config, status, • command, • data }; • struct deviceX *x = BASE_ADDRESS; • x->config = INT_ENABLE|(AL_ON<<1)|(AL_ON<<4)|(25<<8); • stat = x->status; /* Read status */ • while ( !(stat & READY) ) ; • /* Only get here when • READY is set */ • x->command = READ; • ... Usually, you would poll the register until the READY bit is set Anatomy of Modern Processors

  30. Note the NULL statement here! Device Control from HLL • Memory mapped architectures • struct deviceX { • unsigned short config, status, • command, • data }; • struct deviceX *x = BASE_ADDRESS; • x->config = INT_ENABLE|(AL_ON<<1)|(AL_ON<<4)|(25<<8); • stat = x->status; /* Read status */ • while ( !(stat & READY) ) ; • /* Only get here when • READY is set */ • x->command = READ; • while ( !(stat & READY) ); /* Wait again */ • /* Read data */ • data_in = x->data; Usually, you would poll the register until the READY bit is set Anatomy of Modern Processors

  31. Device Drivers in HLL (esp C) • Configuration code • Called from OS or user’s program • Often can use C alone • Commanding device • Again, called from OS or user’s program • Can use C • Responding to device interrupts • Needs an interrupt handler • Slight problem for the ‘assembler-challenged’ • ... Anatomy of Modern Processors

  32. Interrupt Handlers • Processor switches to interrupt handler • As soon as it receives the interrupt signal from a device! • It may be anywhere in some other user’s process • or in the OS • or … • Interrupt handler must save the state of the user’s computation • So that it can restore the processor state to a state identical to that before the interrupt arrived • What defines the state of a computation? • Contents of registers • Status bits (NCVZ etc in PSW) • PC • Contents of memory Anatomy of Modern Processors

  33. Interrupt Handlers • What defines the state of a computation? • Contents of registers • Status bits (NCVZ etc in PSW) • PC • Contents of memory • Memory of other user’s is not generally accessed by an interrupt handler • Maintaining consistent memory is left to the programmer • Processor will push the PC onto the stack before jumping to the interrupt handler • Rather like a procedure call! • Makes the return trivial • Issue iret (return from interrupt) instruction • Registers? Anatomy of Modern Processors

  34. Interrupt Handlers • What defines the state of a computation? • Contents of registers • Status bits (NCVZ etc in PSW) • PC • Contents of memory • Registers? • Interrupt handler must save any registers that it needs to use onto the stack • and • Restore them before the iret • Standard C will not allow explicit access to registers! • Several (simple) lines of assembler are needed to save registers and restore them • Also PSW if interrupt hardware does not handle it itself Anatomy of Modern Processors

  35. Interrupt Handlers • Standard C will not allow explicit access to registers! • Several (simple) lines of assembler are needed to save registers and restore them • Also PSW if interrupt hardware does not handle it itself • Some C development kits provide some extensions to Cwhich allow you to write interrupt handlers entirely in C • The compiler recognises key-words eg • interrupt procedure deviceX_int() { • … • } • The presence of the interrupt key-word causes the compiler to generate code to push all the registers on to the stack on entry to the handler ..and restore them when it’s finished. Anatomy of Modern Processors

  36. Anatomy of Modern Processors

  37. Integrated Processors • Many architectures have variants which contain • A CPU • A collection of peripherals • Memory • Communications interfaces • Parallel I/O • Good for controlling relays, reading switches • A/D and D/A converters • These aim to allow single-chip solutions to embedded processor applications • Use the Si area for devices which reduces • Chip count • Hardware complexity • Manufacturing cost • Allow many interesting portable, low-power, … applications Anatomy of Modern Processors

  38. Cores • What’s a ‘core’? • If you’re designing a high-volume commodity system eg • mobile phone • games console • You want • A high performance processor • Application-specific peripherals, eg • Phone • small display driver • Ring-tone generators • Vibrator • Games console • Analogue position, force, acceleration sensors • Special display • Sound generators Anatomy of Modern Processors

  39. Cores • Commercial constraints • Your product has to be on the market tomorrow! • You can’t afford to waste time designing any ‘standard’ modules • eg the processor! • You need to concentrate on the modules that give you a commercial advantage! • CORES • You buy a processor design from ... • It’s a complete processor design – either • As a schematic (gates, flip-flops, etc) • Written in VHDL • A hardware design language (based on Ada) that describes digital circuits Anatomy of Modern Processors

  40. Cores It’s a complete processor design – either • As a schematic (gates, flip-flops, etc) • Written in VHDL • A hardware design language (based on Ada) that describes digital circuits • This design can be synthesized into a working circuit • ASIC (Application specific integrated circuit) • FPGA (Field programmable gate array) • You add the peripherals around this ‘core’ • and • get your product to market ahead of your competition! Anatomy of Modern Processors

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