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Integrated Circuit Design Lecture 8 (this lecture adopted from © 2002 Prentice Hall). Seungjun Lee Information Electronics Eng. Ewha Womans University. Review. So far, we have reviewed Device characteristics (Ch. 3) Diode and MOS transistor Inverter Basics (Ch. 1) CMOS Inverter (Ch. 5)

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Integrated circuit design lecture 8 this lecture adopted from 2002 prentice hall l.jpg

Integrated Circuit DesignLecture 8(this lecture adopted from © 2002 Prentice Hall)

Seungjun Lee

Information Electronics Eng.

Ewha Womans University


Review l.jpg
Review

  • So far, we have reviewed

    • Device characteristics (Ch. 3)

      • Diode and MOS transistor

    • Inverter Basics (Ch. 1)

    • CMOS Inverter (Ch. 5)

      • Voltage Transfer Characteristic

      • Propagation Delay

      • Power Consumption

      • Impact of Technology Scaling


In this lecture l.jpg
In This Lecture

  • Combinational Logic Design

  • Static CMOS design

    • Complementary CMOS

    • Ratioed Logic

    • Pass-Transistor Logic



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Static CMOS Circuit

  • At every point in time (except during the switching transients) each gate output is connected to either VDD or GND via a low-resistive path.

  • The outputs of the gates assume the value of the Boolean function at all times (ignoring, once again, the transient effects during switching periods).

  • This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance


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NMOS Transistors in Series/Parallel Connection

  • Transistors can be thought as a switch controlled by its gate signal

  • NMOS switch closes when switch control input is high



Threshold drops l.jpg

CL

CL

CL

CL

Threshold Drops

VDD

VDD

S

D

VDD

D

S

0 VDD

0 VDD - VTn

VGS

VDD 0

VDD |VTp|

VGS

D

S

VDD

S

D




Complementary cmos logic l.jpg
Complementary CMOS Logic

PUN: Pull-Up Network

Out

PDN: Pull-Down Network

PUN and PDN are Dual Network

Complementary CMOS gates are ‘inverting’




Example gate complex cmos gate l.jpg
Example Gate: COMPLEX CMOS GATE

Out =





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