FPLDS Introduction. What is Programmable Logic?. Circa 1970 -- TTL Design. Design a logic circuit that implements the function. 74HC04. 74HC32. 74HC08. Design is done “by hand” using TTL DataBook. Verification is performed using a “breadboard.”. TTL Design.
Circa 1970 -- TTL Design
Design a logic circuit that implements the function
Design is done “by hand” using TTL DataBook.
Verification is performed using a “breadboard.”
We need three separate Dual Inline Package (DIP) TTL packages to implement this design in hardware. Note, because of the multiple components this design consumes power, board space is costly, hard to debug and manufacture.
In field programmable logic device (FPLD) design (FPLD), we use a computer aided design (CAD) software tool (e.g. QUARTUS II) to perform “design entry.” We can also use the same package for “design verification” and also to “download” the “design program” into hardware (i.e. the PLD). Our design
This single chip design requires
Less power, less board space,
should cost less on a per gate
basis, is easier to debug (in software),
and be easier to manufacture. Also,
Intellectual Property (IP) can be protected and exploited using a FPLD.
Large Delay on this net
The same net
is now internal
to the FPLD
at each node. Blue dot means
a connection has been made.
We can use a PAL to implement Sum-of-Products (SOP) Logic
Use a PAL to design a logic circuit which implements
Note: In our PAL, we have the “fixed” logic
Let’s “program” the AND Array (or AND plane), so that
We can use the same type of device to “program”
However, what if, I want
I’ve run out of pterms!!! Need to pick a bigger PAL!!!
Add programmable I/O “macrocells” to PAL architecture.
I/O Macrocells contain registers.
“Mini” PALs, programmable with registers called
Logic Array Blocks (LABS) are interconnected using
a Programmable Interconnect Array (PIA).
LAB=Logic Array Block (prog)
PIA = Prog. Interconnect Array
An array of “small” blocks of programmable logic within an
LCs to routing
I/O = Input/Output Cell
Combines Programmable Logic with embedded Static
Random Access Memory (SRAM) on the same Integrated
Altera and Xilinx
PEs are used to physically “program” the interconnects.
FET acts like a “switch”
If Vgate is ONE, switch is closed, connecting A and B otherwise A and B are isolated.
Field Effect Transistor (FET)
So, we’ll have one FET at every programmable
Interconnect, but we need a method or technique
to “program” VGATE to be ONE or ZERO.
Before, we look at our options, some definitions
“Program” is lost when power is removed
“Program” is retained with power is removed.
PE can be “erased” and “re-programmed”
2. One-time-programmable (OTP)
PE can only be programmed “one” time.
(not really used anymore)
EPROM – Erasable Programmable Read Only Memory
Reprogrammable and non-volatile
It is possible to physically program an EPROM cell to always be ONE when power is applied. Also, we can use ultraviolet (UV) light to reset or “erase” the EPROM cell back to ZERO.
We can, therefore, erase all the cells of the EPROM
and then program the PEs that we want to be ONEs.
EEPROM – (E2PROM)
Electrically Erasable Programmable Read Only Memory
Reprogrammable and non-volatile
Similar to an EPROM except cell can be “erased” electrically.
Ex: MAX-7000 family
Store the value of VGATE within a SRAM cell. We lose
the program whenever the power is removed. Therefore,
we’ll need the ability to “reload” the design upon power-up.
WL=1, turns “ON” FET, connecting BL to the cell
WL=0, turns “OFF” FET, isolating data from the cell.
However, Due to “positive” feedback, data is retained in the memory cell until power is removed
Use a SRAM cell to store VGATE. Lose “program” when
power is removed.
Non-volatile and OTP
Normally, anti-fuse behaves like an “open” circuit, however you can “destroy” the fuse electrically so that it behaves like a short circuit.
The antifuse is very small compared to the
IGeneric FPLD Design
At a minimum, every FPLD needs
1. Programmable Logic (L)
2. Programmable Interconnects (I)
3. Input/Output Logic (I/O)
IGeneric FPLD Design
1/3 Logic, 1/3 Interconnects, 1/3 Input/Output
Do I have enough logic?
1/2 Logic, 1/4 Interconnects, 1/4 Input/Output
Logic is good, but now do I have enough
interconnects for my logic?
1/4 Logic, 1/2 Interconnects, 1/4 Input/Output
Ok, I have enough interconnects for my
logic. Do I have enough I/O?
Different vendors use different approaches
Let’s examine Altera MAX and Altera Flex!!!
BST = Built-in Self Test - ISP – In-system programmability
Similar to sharable expanders
Up to 20 pterms in one MC
SRAM as PEs, reprogrammable and volatile
Example 2 bit multiplier Y = AxB
A1B1 A0B1 0
S3 S2 S1 S0
Where S0 = A0B0
S1 = A1B0 + A0B1
S2 = A1B1 +Carry_S1
S3 = Carry_S2
Example 2 bit multiplier Y = 11x11
1 1 0
1 0 0 1
3x3 = 9
12x2 Bit Multiplier
16 x 4
LUT contains the “Truth table” of the design
Let A=11 and B=11
Worst Case Delay = tgate + 2*tfa
16 x 4 SRAM
Tdelay = t_LUT_access
Quartus allows access to EABs through the use of Linear Parameterized Modules (LPMs).
Let’s look at various memory arrays available through Quartus.
A ROM has “pre-loaded” data that is not intended to change overtime. Traditionally, ROMs are used to store program code in a computer system. However, we can also use a ROM as a giant look-up table (LUT) to perform functional translations on our data.
There are two basic access modes we will need to
1. Asynchronous mode
2. Synchronous mode
Note: Apply X to address bus, tacc seconds later
the value of Y appears on Q.
Tacc = data access time
We can add a clock to make the ROM access
Apply X to address bus, tsu (setup) seconds before the clock
edge. The value of Y will appear on Q, tacc seconds
after the clock edge.
Example: Let’s Implement the function
y=2x + 5
We could design a circuit to perform this calculation, but it may
be more efficient to “pre-load” a ROM with the answer to every
possible input value of x.
Note: we’ll need a 2n x W ROM where n is the number of
bits in x and W is the number of bits needed to represent
the maximum value of y.
Let x = 3 bits. Range of x is 0 to 7.
Max Y = 2(7)+5 =19 W=5 bits
So, we will need a 3x5 bit ROM
A single port SRAM allows data to be read and written into the memory array by the user. In general a single port has the following input/output lines:
The control line is needed to determine which access mode
we will need. This can be read mode or write mode.
Single port means we use a single port to interface to the RAM
Data Input Bus
Data Output Bus
R/W = 1 : Read mode
R/W = 0 : Write mode
Let’s look at an internal block diagram of the SRAM
Tacc = access time
Tasu,tahd = address setup and hold times
Tdsu,tdhd = data setup and hold times
Twp = write pulse time
A dual port SRAM allows data to be read from one port and written to another port.
You can read
and write to both
ports simultaneously as
long as you are not using
the same address.
This is not a “true” dual port
First-in First-out Buffer
Input Data Port
Output Data port
Write request port
Read request port
Buffer empty signal