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FPLDS Introduction. What is Programmable Logic?. Circa 1970 -- TTL Design. Design a logic circuit that implements the function. 74HC04. 74HC32. 74HC08. Design is done “by hand” using TTL DataBook. Verification is performed using a “breadboard.”. TTL Design.

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Fplds introduction

FPLDS Introduction


What is programmable logic

What is Programmable Logic?

Circa 1970 -- TTL Design

Design a logic circuit that implements the function

74HC04

74HC32

74HC08

Design is done “by hand” using TTL DataBook.

Verification is performed using a “breadboard.”


Ttl design

TTL Design

We need three separate Dual Inline Package (DIP) TTL packages to implement this design in hardware. Note, because of the multiple components this design consumes power, board space is costly, hard to debug and manufacture.


Fpld design

FPLD Design

In field programmable logic device (FPLD) design (FPLD), we use a computer aided design (CAD) software tool (e.g. QUARTUS II) to perform “design entry.” We can also use the same package for “design verification” and also to “download” the “design program” into hardware (i.e. the PLD). Our design

now becomes:

This single chip design requires

Less power, less board space,

should cost less on a per gate

basis, is easier to debug (in software),

and be easier to manufacture. Also,

Intellectual Property (IP) can be protected and exploited using a FPLD.


Benefits of fpld design

Benefits of FPLD Design

  • Increased system performance (Speed)

    • This is due to the reduced interconnect distances between gates. In a

    • TTL design we have large RC delays as we propagate signals from one chip

    • to another. In FPLD designs, this distances are in the um range.

Large Delay on this net

FPLD Design

The same net

is now internal

to the FPLD


Benefits of fpld design1

Benefits of FPLD Design

  • Increased Gate Density

    • More logic gates on each FPLD implies that you can have more functionality per unit area of board space. A single FPLDs/FPGAs can hold the equivalent of over 1 million TTL logic gates.

  • Reduced Development Time

    • CAD tools significantly reduce the development time for new designs. This not only cuts down the “time to market,” but also allows reduces the size of the team needed to complete a design.


Benefits of fpld design2

Benefits of FPLD Design

  • Rapid Hardware Prototyping

  • Hardware prototyping is greatly simplified using FPLDs because it is relatively easy to change the design. One major concern however is I/O pin assignments.

  • Reduced “Time to Market”

    • Since FPLDs are already “complete,” there is no need to wait for fabrication.


Benefits of fpld design3

Benefits of FPLD Design

  • Future Modifications

  • Since FPLDs can be “reconfigured” in the field. It is possible to have the end user perform system “upgrades.”

  • Reduced Inventory Risk

    • The same type of FPLD can be used in multiple

    • designs, so the inventory risk is significantly reduced.


Benefits of fpld design4

Benefits of FPLD Design

  • Reduced Development Costs

  • The development costs for FPLDs tend to be lower than Application Specific Integrated Circuits (ASICs); however, the per unit cost of a FPLD is higher than an ASIC for large volumes.


Shorthand notation

Shorthand Notation

Programmable Interconnect

at each node. Blue dot means

a connection has been made.


Shorthand notation cont

Shorthand Notation (Cont)


Programmable logic array pal

Programmable Logic Array (PAL)

AND-OR Architecture

Inputs

Outputs


Pal example

PAL Example

P

R

O

D

U

C

T

AND

Plane

(Prog)

T

E

R

M

S

OR

Plane

(Fixed)

SUM TERMS


Pal example1

PAL Example

We can use a PAL to implement Sum-of-Products (SOP) Logic

Example:

Use a PAL to design a logic circuit which implements

Note: In our PAL, we have the “fixed” logic


Pal example2

PAL Example

Let’s “program” the AND Array (or AND plane), so that

Since,

We find,


Pal example3

Programmable

Interconnects

PAL Example

AND

Plane

(Prog)

OR

Plane

(Fixed)


Pal example4

PAL Example

We can use the same type of device to “program”

Let


Pal example5

Programmable

Interconnects

PAL Example

OR

Plane

(Fixed)


Pal example6

What about

term?

PAL Example

However, what if, I want

Let

I’ve run out of pterms!!! Need to pick a bigger PAL!!!


Survey of fplds pals

Survey of FPLDs PALs

Ex: 16V8

Circa: 1978

Inputs

Outputs


Survey of fplds simple plds

Survey of FPLDs Simple PLDs

Add programmable I/O “macrocells” to PAL architecture.

I/O Macrocells contain registers.

Ex: 22V10

Circa:

1980


Survey of fplds complex plds

Survey of FPLDs Complex PLDs

“Mini” PALs, programmable with registers called

Logic Array Blocks (LABS) are interconnected using

a Programmable Interconnect Array (PIA).

Altera’s

Max-5032

Max-7032

Circa:

1985

LAB=Logic Array Block (prog)

PIA = Prog. Interconnect Array


Survey of fplds field programmable gate arrays fpgas

Survey of FPLDs Field Programmable Gate Arrays (FPGAs)

An array of “small” blocks of programmable logic within an

Vendors

Xilinx

(Actel)

Circa:

1990

Programmable

Interconnects

Connects

LCs to routing

channels

Routing

Channels

I/O = Input/Output Cell

LC=Logic Cell


Survey of fplds system on programmable chip sopc

Survey of FPLDs System-on Programmable Chip (SOPC)

Combines Programmable Logic with embedded Static

Random Access Memory (SRAM) on the same Integrated

Circuit (IC).

Circa:

2000

to

Now!!

Altera and Xilinx


Programming elements pe

Programming Elements - PE

PEs are used to physically “program” the interconnects.

FET acts like a “switch”

If Vgate is ONE, switch is closed, connecting A and B otherwise A and B are isolated.

Field Effect Transistor (FET)


Programming elements pe1

Programming Elements - PE

Example

Closed

Open

Vgate=One

Switch Closed

Vgate=Zero

Switch Open


Programming elements pe2

Programming Elements - PE

So, we’ll have one FET at every programmable

Interconnect, but we need a method or technique

to “program” VGATE to be ONE or ZERO.

Before, we look at our options, some definitions


Programming elements pe3

Programming Elements - PE

Two Types:

1. Volatile

“Program” is lost when power is removed

2. Non-volatile

“Program” is retained with power is removed.

Two Classes:

1. Re-programmable

PE can be “erased” and “re-programmed”

2. One-time-programmable (OTP)

PE can only be programmed “one” time.

(not really used anymore)


Programming technologies

Programming Technologies

EPROM – Erasable Programmable Read Only Memory

Reprogrammable and non-volatile

It is possible to physically program an EPROM cell to always be ONE when power is applied. Also, we can use ultraviolet (UV) light to reset or “erase” the EPROM cell back to ZERO.

Ex: Max-5000


Programming technologies eprom

Programming TechnologiesEPROM

UV

To erase

We can, therefore, erase all the cells of the EPROM

and then program the PEs that we want to be ONEs.


Programming technologies1

Programming Technologies

EEPROM – (E2PROM)

Electrically Erasable Programmable Read Only Memory

Reprogrammable and non-volatile

Similar to an EPROM except cell can be “erased” electrically.

Ex: MAX-7000 family


Programming technologies2

Programming Technologies

  • SRAM

  • Static Random Access Memory

    • Volatile and Reprogrammable (electrically)

SRAM

Cell

To Vgate

Store the value of VGATE within a SRAM cell. We lose

the program whenever the power is removed. Therefore,

we’ll need the ability to “reload” the design upon power-up.


Sram cell write

SRAM CELLWrite

Write 0

Write 1

1

0

1

0

0

0

1

1

1

1

WL=1, turns “ON” FET, connecting BL to the cell


Sram cell read

SRAM CELLRead

Read

X

data

data

data

0

WL=0, turns “OFF” FET, isolating data from the cell.

However, Due to “positive” feedback, data is retained in the memory cell until power is removed


Programming technologies sram

Programming TechnologiesSRAM

Use a SRAM cell to store VGATE. Lose “program” when

power is removed.


Programming technologies3

Programming Technologies

Anti-Fuse

Non-volatile and OTP

Normally, anti-fuse behaves like an “open” circuit, however you can “destroy” the fuse electrically so that it behaves like a short circuit.

Anti-fuse

The antifuse is very small compared to the

other PEs.

.


Summary fpld benefits

Summary FPLD Benefits

  • Increased Performance

  • Increased Gate Density

  • Reduced Development Time

  • Rapid Hardware Prototyping

  • Reduced “Time to Market”

  • Future Modifications

  • Reduced Inventory Risks

  • Reduced Development Costs


Summary fpld types

Summary FPLD Types

  • PALS

  • Simple PLDs

  • Complex PLDs (FPLDs)

  • FPGAs

  • SOPC


Summary programming elements

Summary Programming Elements

Types:

Classes:

  • Reprogrammable

  • OTP

  • Volatile

  • Non-Volatile

Technologies:

  • EPROM (Obsolete)

  • EEPROM

  • Anti-Fuse

  • SRAM


Summary programming elements1

Summary Programming Elements


Generic fpld design

I/O

L

I

Generic FPLD Design

At a minimum, every FPLD needs

1. Programmable Logic (L)

2. Programmable Interconnects (I)

3. Input/Output Logic (I/O)

FPLD


Generic fpld design1

I/O

L

I

Generic FPLD Design

1/3 Logic, 1/3 Interconnects, 1/3 Input/Output

FPLD

Do I have enough logic?


Generic fpld design2

Generic FPLD Design

1/2 Logic, 1/4 Interconnects, 1/4 Input/Output

FPLD

L

I

I/O

Logic is good, but now do I have enough

interconnects for my logic?


Generic fpld design3

Generic FPLD Design

1/4 Logic, 1/2 Interconnects, 1/4 Input/Output

FPLD

L

I

I/O

Ok, I have enough interconnects for my

logic. Do I have enough I/O?


Generic fpld design4

Generic FPLD Design

Different vendors use different approaches

FPLD

L

I

I/O

Let’s examine Altera MAX and Altera Flex!!!


Altera max 7000

Altera Max-7000


Altera max 7000 device family

Altera MAX-7000 Device Family

  • EEPROM used as PE

    • Non-volatile and Re-programmable


Definitions

Definitions

  • Useable gates

    • Number of equivalent TTL NAND gates

  • Macrocells

    • Number of unique mini PALs

  • Maximum user I/O Pins

  • Tpd = Input to non-registered output

  • Tsu = External global clock register setup time

  • Tfsu = External fast input register setup time

  • Tco1 = Global clock to output delay

  • Fcnt (MHz) = Maximum 16 bit up/down counter freq


Max 7000s block diagram

MAX-7000S Block Diagram


Block diagram notes

Block Diagram Notes

  • Global clocks

  • Global reset

  • Global Output Enable

  • Global Inputs

  • PIA - Programmable Interconnect Array

  • LABs – Logic Array Blocks

    • Macrocells are contained in LABs


Max 7000 device features

MAX-7000 Device Features

BST = Built-in Self Test - ISP – In-system programmability


Max 7000 features cont

MAX-7000 Features (cont)


Max 7000s macrocell

MAX-7000S Macrocell


Macrocell notes

Macrocell Notes

  • Macrocell is customizable

  • Local and Global Clocks

    • Global clock used if no logic added to clock line

  • Register bypass for combinational logic designs

  • One programmable register per MC

    • D, T, JK or SR operation

    • Enable function

    • Preset and reset functions

  • Sharable expanders allow extra pterm to be “shared” with another macrocell


Sharable expanders

Sharable Expanders


Parallel expanders

Parallel Expanders

Similar to sharable expanders

Up to 20 pterms in one MC


Altera flex 10k

Altera Flex 10K


Altera flex 10ke device features

AlteraFlex 10KE Device Features

SRAM as PEs, reprogrammable and volatile


Acronyms

Acronyms

  • SOPC – System on a Programmable Chip

  • LE – Logic Elements

    • Core logic block

  • LAB – Logic Array Block

  • EAB – Embedded Array Block

    • On Chip SRAM


Features cont

Features (cont)


Device performance metrics

Device Performance Metrics


Flex 10ke block diagram

Flex 10KE Block Diagram


Block diagram notes1

Block Diagram Notes

  • Still have LABs, but MC replaced with LE

    • Each LAB has eight (8) LEs

  • Embedded memory stored in EABs

    • Asynchronous and Synchronous modes


Flex 10ke logic element

Flex 10KE Logic Element


Logic element le notes

Logic Element (LE) Notes

  • LUT – Look Up Table has replaced MC

    • 4 inputs: 16 x 1 SRAM Array

  • Register bypass for combinational logic designs

    • Register packing -

    • LUT and register can be used for different functions

  • One programmable register per LE

    • D, T, JK or SR operation

    • Enable function

    • Preset and reset functions

  • High-speed carry and cascade chains


Look up tables luts

Look Up Tables (LUTS)


Why use a lut for logic implementation

Sum

Why use a LUT for logic implementation?

Example 2 bit multiplier Y = AxB

A1 A0

B1 B0

A1B0 A0B0

A1B1 A0B1 0

S3 S2 S1 S0

Where S0 = A0B0

S1 = A1B0 + A0B1

S2 = A1B1 +Carry_S1

S3 = Carry_S2


Example

Example

Example 2 bit multiplier Y = 11x11

1 1

1 1

1 1

1 1 0

+

1 0 0 1

3x3 = 9


Let s implement this using logic gates

Let’s implement this using Logic Gates

Full Adder

Symbol


2x2 bit multiplier

1

3

1

1

3

9

1

2x2 Bit Multiplier

1

1

0

1

1

0

1

1


Same design using a lut

Same Design using a LUT

  • LUT = Look Up Table

S3

A1

S2

A0

LUT

S1

B1

S0

B0

16 x 4

Outputs

Inputs

LUT contains the “Truth table” of the design


Lut design

LUT Design

A[1..0]

S[3..0]

B[1..0]


Lut example

LUT Example

Let A=11 and B=11

S[3..0]=1001

A[1..0]=11

B[1..0]=11


2x2 bit multiplier delay calculation

2x2 Bit MultiplierDelay Calculation

Worst Case Delay = tgate + 2*tfa


Lut delay calculation

LUTDelay Calculation

  • LUT = Look Up Table

S3

A1

S2

A0

LUT

S1

B1

S0

B0

16 x 4 SRAM

Tdelay = t_LUT_access


Memory arrays

.

Memory Arrays


Memory arrays1

Memory Arrays

  • We can combine memory cells into memory arrays.

  • Memory arrays used to store

    • State information

    • Data information

    • Startup information


Linear parameterized modules lpms

Linear Parameterized ModulesLPMs

Quartus allows access to EABs through the use of Linear Parameterized Modules (LPMs).

Let’s look at various memory arrays available through Quartus.


Memory arrays2

Memory Arrays

  • Read-Only Memory (ROM)

  • Single Port SRAM

  • Dual Port SRAM

  • First-in First-out (FIFO) SRAM

  • Last-in First-out (LIFO) “Stack”

  • Content Addressable Memory (CAM)


Fplds introduction

ROMs


Read only memory rom

Read Only Memory (ROM)

A ROM has “pre-loaded” data that is not intended to change overtime. Traditionally, ROMs are used to store program code in a computer system. However, we can also use a ROM as a giant look-up table (LUT) to perform functional translations on our data.

There are two basic access modes we will need to

examine:

1. Asynchronous mode

2. Synchronous mode


Lpm rom implementation

LPM_ROM Implementation

Asynchronous mode

X

Y


Timing diagram read mode asynchronous access

Timing DiagramRead Mode Asynchronous Access

Note: Apply X to address bus, tacc seconds later

the value of Y appears on Q.

Tacc = data access time


Lpm rom implementation1

LPM_ROM Implementation

Synchronous access

X

Y

clock

We can add a clock to make the ROM access

synchronous.


Timing diagram read mode synchronous access

Timing DiagramRead Mode Synchronous Access

Apply X to address bus, tsu (setup) seconds before the clock

edge. The value of Y will appear on Q, tacc seconds

after the clock edge.


Rom example

ROM Example

Example: Let’s Implement the function

y=2x + 5

We could design a circuit to perform this calculation, but it may

be more efficient to “pre-load” a ROM with the answer to every

possible input value of x.

Note: we’ll need a 2n x W ROM where n is the number of

bits in x and W is the number of bits needed to represent

the maximum value of y.


Rom example y 2x 5

ROM Example: Y=2x+5

Let x = 3 bits. Range of x is 0 to 7.

Max Y = 2(7)+5 =19  W=5 bits

So, we will need a 3x5 bit ROM

ROM Table


Lpm rom

LPM_ROM


Quartus ii design

QUARTUS II Design

SIMULATION


Single port sram

Single Port SRAM


Single port sram1

Single Port SRAM

A single port SRAM allows data to be read and written into the memory array by the user. In general a single port has the following input/output lines:

  • Data Input bus

  • Data Output bus

  • R/W Control line

  • Address bus

The control line is needed to determine which access mode

we will need. This can be read mode or write mode.

Single port means we use a single port to interface to the RAM


Static random access memory sram array symbol

Static Random Access Memory(SRAM) Array Symbol

Data Input Bus

Din[n-1..0]

Data Output Bus

Add[n-1..0]

Address Bus

Dout[n-1..0]

R/W

Read/Write

Control Line

R/W = 1 : Read mode

R/W = 0 : Write mode

Let’s look at an internal block diagram of the SRAM


Fplds introduction

Block Diagram of SRAM

4x4


Timing diagram read mode access asynchronous

Timing DiagramRead Mode AccessAsynchronous

Tacc = access time


Fplds introduction

Block Diagram of SRAM

Add=10

1

Read Mode


Timing diagram write mode access asynchronous

Timing DiagramWrite Mode AccessAsynchronous

Tasu,tahd = address setup and hold times

Tdsu,tdhd = data setup and hold times

Twp = write pulse time


Fplds introduction

Block Diagram of SRAM

Add=10

0

Write Mode


Lpm ram dq

LPM_RAM_DQ


Dual port sram

Dual Port SRAM


Dual port sram1

Dual Port SRAM

A dual port SRAM allows data to be read from one port and written to another port.

You can read

and write to both

ports simultaneously as

long as you are not using

the same address.

Read Port

Write Port

This is not a “true” dual port


Fplds introduction

FIFO

First-in First-out Buffer


Fifo buffer

FIFO Buffer

  • A first-in first-out (FIFO) buffer is used to synchronize two data streams that are processing data at different rates. Note: the “average” data rates of both sides have to be equivalent.

  • As the name implies, the first data byte written on the input side(First-in) is the first data byte read on the output side (First-out).


Lpm fifo

LPM_FIFO

Input Data Port

Output Data port

Write request port

Read request port

Clock

Buffer empty signal

Asynch reset


Content addressable memory cam

Content Addressable Memory (CAM)


Fplds introduction

CAMS

  • Content Addressable Memory (CAM)

    • A CAM is an “inverse” RAM. That is, you provide input data and the CAM provides the address location of the data.

Address

DATA

CAM


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