CMOS Detector Technology

1. CMOS Detector Technology Markus Loose Rockwell Scientific Vyshnavi Suntharalingam MIT Lincoln Laboratory Alan Hoffman Raytheon Vision Systems Scientific Detector Workshop, Sicily 2005

2. Photodiode Photodiode Amplifier + Pixel Charge generation, charge integration & charge-to-voltage conversion Charge generation & charge integration Multiplexing of pixel voltages: Successively connect amplifiers to common bus Array Readout Charge transfer from pixel to pixel • Various options possible: • no further circuitry (analog out) • add. amplifiers (analog output) • A/D conversion (digital output) Sensor Output Output amplifier performs charge-to-voltage conversion General CMOS Detector Concept CCD Approach CMOS Approach

3. Common CMOS Features • CMOS sensors/multiplexers utilize the same process as modern microchips • Many foundries available worldwide • Cost efficient • Latest processes available down to 0.13 µm • CMOS process enables integration of many additional features • Various pixel circuits from 3 transistors up to many 100 transistors per pixel • Random pixel access, windowing, subsampling and binning • Bias generation (DACs) • Analog signal processing (e.g. CDS, programmable gain, noise filter) • A/D conversion • Logic (timing control, digital signal processing, etc.) • Electronic shutter (snapshot, rolling shutter, non-destructive reads) • No mechanical shutter required • Low power consumption • Radiation tolerant (by process and by design)

4. Full field row Window Full field row Full field row Full field row Full field row Window Window Astronomy Application: Guiding • Special windowing can be used to perform full-field science integration in parallel with fast window reads. • Simultaneous guide operation and science data capture within the same detector. • Two methods possible: • Interleaved reading of full-field and window • No scanning restrictions or crosstalk issues • Overhead reduces full-field frame rate • Parallel reading of full-field and window • Requires additional output channel • Parallel read may cause crosstalk or conflict • No overhead  maintains maximum full-field frame rate

5. horiscan1 horiscan2 V 1 array array array V 2 array array array horiscan2 horiscan1 V 3 array array array V 1 V 2 V 3 array Stitching Enables Large Sensor Arrays • The small feature size of modern CMOS processes limits the maximum area that can be exposed in one step (so-called reticle) to about 22 mm. • However, larger chips can produced by breaking up the design into smaller sub-blocks that fit into the reticle. Stitched CMOS Sensor • Sub-blocks are exposed one after another • Some blocks are used multiple times • Ultimate limit is given by wafer size Reticle 22mm

6. Reset SF PD Select Read Bus Reset SF TG Pinned PD p+ n+ n+ p-sub Select Read Bus Monolithic CMOS • A monolithic CMOS image sensor combines the photodiode and the readout circuitry in one piece of silicon • Photodiode and transistors share the area => less than 100% fill factor • Small pixels and large arrays can be produced at low cost => consumer applications (digital cameras, cell phones, etc.) 3T Pixel photodiode transistors 4T Pixel

7. 2 Mpixel HDTV CMOS Sensor Quantum Efficiency of a CMOS sensor Si PIN NIR AR coating Si PIN UV AR coating • Microlenses increase fill factor: 3T pixel w/ microlenses photodiode Complete Imaging Systems-on-a-Chip • Monolithic CMOS technology has enabled highly integrated, complete imaging systems-on-a-chip: • Single chip cameras for video and digital still photography • Performance has significantly improved over last decade and is better or comparable to CCDs for many applications. • Especially suited for high frame rate sensors (> Gigapixel/s) or other special features (windowing, high dynamic range, etc.) • However, monolithic CMOS is still limited with respect to quantum efficiency: • Photodiode is relatively shallow => low red response • Metal and dielectric layers on top of the diode absorb or reflect light => low overall QE • Backside illumination possible, but requires modification of CMOS process

8. Mature interconnect technique: Over 4,000,000 indium bumps per SCA demonstrated 99.9% interconnect yield Detector Array Detector Array Indium bump 16,000,000 Sensor Chip Assembly (SCA) Structure:Hybrid of Detector Array and ROIC Connected by Indium Bumps Silicon Readout Integrated Circuit (ROIC) • Also called a Focal Plane Array (FPA) or Hybrid Array

9. CMOS SCA Revolution • Large CMOS hybrids revolutionized infrared astronomy • Growth in size has followed "Moore's Law" for over 20 years • 18 month doubling time

10. Three Most Common Input Circuits for CMOS ROICs Circuit SFD (Source Follower per Detector) also called "Self Integrator" CTIA (Capacitance Transimpedance Amplifier) DI (Direct Injection) • Advantages • simple • low noise • low FET glow • low power • very linear • gain determined by ROIC design (Cfb) • detector bias remains constant • large well capacity • gain determined by ROIC design (Cint) • detector bias remains constant • low FET glow • low power • Disadvantages • gain fixed by detector and ROIC input capacitance • detector bias changes during integration • some nonlinearity • more complex circuit • FET glow • higher power • poor performance at low flux Comments Most common circuit in IR astronomy Very high gains demonstrated Standard circuit for high flux

11. Si PIN InGaAs SWIR HgCdTe MWIR HgCdTe InSb LWIR HgCdTe Si:As IBC Temperature and Wavelengths ofHigh Performance Detector Materials Approximate detector temperatures for dark currents << 1 e-/sec

12. Detector Material Choices for CMOS Hybrid Arrays Spectral Range*, m 0.4 – 1.0 0.9** – 1.7 0.9** – 1.7 0.9** – 2.5 0.9** – 5.2 5 – 10 0.4 – 5.2 5 – 28 Operating Temp***, K ~ 200 ~ 130 ~ 140 ~ 90 ~ 50 ~ 25? ~ 35 ~ 7 • General Comments • All detectors can have: • 100% optical fill factor • 100% internal QE (total QE depends on AR coat) • Exception: Si:As is 40-70% between 5 and 10 m • ROICs are interchangeable among detectors (except Si:As) • HgCdTe and InGaAs require special packaging due to CTE mismatch between detector and ROIC Detector Material Si PIN InGaAs HgCdTe: 1.7m 2.5 m 5.2 m 10 m InSb Si:As IBC (BIB) * Long wave cutoff is defined as 50% QE point ** Spectral range can be extended into visible range by removing substrate *** Approximate detector temperatures for dark currents << 1 e-/sec

13. Process Comparison 2mm 2mm 2mm Four-Poly OTCCD 180-nm SRAM cell Stacked via to poly

14. photodiode OUT RST VDD ROW VDD ROW OUT RST n+ p+ Field Oxide n-Well p-well p-epi p+ Substrate Limitations of Standard Bulk CMOS APS Pixel Layout • Fill factor tradeoff • Photodetector and pixel transistors share same area • PD from Drain-Substrate or Well-Substrate diode • Low photoresponsivity • Shallow, heavily doped junctions • Limited depletion depth • Absorption and reflection in poly, metal, and oxide layers • Surface recombination at Si/SiO2 interface • QE*FF > 60% is good, many < 20% • High leakage • LOCOS/STI, salicide • Transistor short channel effects • Substrate bounce and transient coupling effects

15. pixel Advantages of Vertical Integration Conventional Monolithic APS 3-D Pixel Light • Pixel electronics and detectors share area • Fill factor loss • Co-optimized fabrication • Control and support electronics placed outside of imaging area PD pixel PD 3T Addressing ROIC Processor Addressing A/D, CDS, … • 100% fill factor detector • Fabrication optimized by layer function • Local image processing • Power and noise management • Scalable to large-area focal planes

16. 10 mm 10 mm 10 mm Approaches to 3D Integration (To Scale) Tier-1 3D-Vias 3D-Vias Tier-2 Photo Courtesy of RTI Bump Bond used to flip-chip interconnect two circuit layers Two-layer stack using Lincoln’s SOI-based vias Two-layer stack with insulated vias through thinned bulk Si

17. Comparison CMOS vs. CCD for Astronomy Silicon PIN hybrid detectors have become a serious alternative to CCDs providing a number of significant advantages, specifically for large mosaic focal plane arrays.