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Week12

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  1. Week12 Interrupts on the 8051

  2. What is an interrupt? An interrupt is an event that forces the CPU to temporarily stop what its doing and transfer control to an interrupt service routine (ISR), which returns upon completion • Compared to the CPU initiated data transfer, using interrupts is a more efficient and a common way of handling I/O. • This is because CPU does not have to wait for I/O to be ready. • An interrupt is an I/O initiated data transfer and is performed only when the I/O device is ready for the transfer. • Interrupts are typically used to • allow handling and recovery from catastrophic events • handle events not normally associated with program execution • handle events that occur at a slow rate • handle requests from I/O devices

  3. Interrupts Main Program An "Interrupt" is a break in the flow of execution of a program. Can occur at any point. CPU is "interrupted" while executing program. When an interrupt occurs, the CPU deals with the interruption, then carries on where it left off as shown ISR

  4. Polling vs. Interrupts Polling Interrupts • Software in control • Simple • CPU in charge, • CPU asks device .. • In-efficient in any, but the simplest system • I/O device requests service when needed • CPU only attends to I/O device when it needs service • More efficient than polling • Excess use of interrupts will slow program down

  5. CPU IRQ Types of Interrupts • There are two distinct types of interrupts. • The first type is a hardware interrupt. This is an interrupt which is initiated by an external signal • For example an I/O device requests an interrupt by taking an Interrupt Request line (IRQ) active. • The CPU sees the Interrupt Request and executes the interrupt service routine. • Hardware interrupts are typically used to deal with I/O devices which need attention • Hardware interrupts can be classified as • Non Maskable   interrupt is initiated through hardware and cannot be disabled • Maskable interrupt is initiated through hardware, but can be enabled or disabled through software


  6. Types of Interrupts • Second type is software interrupt • One example is an interrupt that is initiated by a dedicated software instruction. Program can generate interrupt using special interrupt instruction. Also called traps. • The resulting interrupt is dealt with in the same way as a hardware interrupt. • An example for the 80x86 CPU is the instruction INT 4 ; 80x86 instruction • which forces an interrupt to occur. • Other instructions can cause an interrupt to occur in certain circumstances. An example is the DIV instruction on the 80x86. Such interrupts are called exceptions. • What happens when a software and hardware interrupt occurs at the same time? • The answer is that the CPU has a preassigned prioritydefined for such an event.

  7. Interrupt Processing

  8. Location of ISR • How does the CPU know where the lcoation of the ISR is? • There are 3 possibilities • Fixed ISR locations • Here the CPU loads the PC with a predefined address when an interrupt occurs • The ISR code must always start at this predefined address • Vector table • This is a group of memory locations that contain the actual addresses for each ISR • When an interrupt occurs, the CPU loads the PC with ISR address at the relevant location in the vector table • The contents of the vector table can be changed, by loading different ISR addresses. • This makes it easy to change the ISR for a particular interrupt source • Interrupting device supplies interrupt vector • Here, the interrupting device supplies an interrupt vector (typically a byte) after it requests an interrupts. This byte can then be used to create the address for the ISR • Because the I/O device must supply the interrupt vector, the I/O device is therefore more complex. However, this approach yields the most flexibility

  9. General points about ISRs • should be short • Interrupt can occur at any time, so the program should have no idea that it was interrupted. • ISRs can be interrupted • Proper assignment of priorities • Operating systems (such as Linux or Windows) will impose additional OS specific steps for writing ISRs Writing an ISR • Save ALL registers you modify (Push to stack) • Enable interrupts (allow higher priority interrupts to occur)* • Service hardware that caused the interrupt • Respond to the specifics of the I/O device • Clear interrupting flag (so same interrupt won’t occur after completion of ISR). May occur automatically* • Reset Programmable Interrupt Controller (PIC), if one is used* • Output 20H to I/O port 20H ; send EOI to PIC • Restore Registers with original values (POP) • IRET: Pop Flags & return * Relates to optional steps, depending on the CPU used and the interrupt hardware for the system With 8051, always save PSW and ACC. Can use bank switching Use RETI

  10. Return from interrupt • Control is transferred to an ISR just like a call to a normal subroutine • Return address is pushed on the stack • Some CPUs also push other specific registers, that are not saved on the stack with normal subroutine calls • The IRET (return from interrupt) instruction is used to return from the ISR • Pops the return address off the stack into the PC • Restores any specific registers that were automatically saved when the ISR started • Performs hardware specific clean up related functions

  11. Initialisation of ISRs • Disable interrupts • Store ISR addresses in vector table (if used) • Initialise interrupt hardware • Interrupt Controller & I/O device(s) • Clear any pending interrupts • Clear any buffers used by ISRs • Assign priorities • Enable interrupts and start main loop

  12. Interrupts on the 8051 • The 8051 has 2 external interrupts and 3 internal interrupts. The 2 external interrupt lines are shown below, along with the RST (reset) line. • Total of 5 interrupting sources • Each can be individually disabled or enabled • The internal interrupts can be generated by • Timer0 • Timer1 • UART INT0 INT1 RST

  13. 7 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TCON

  14. 7 7 0 0 EA - - - - - PS ES ET1 PT1 EX1 PX1 PT0 ET0 PX0 EX0 Interrupt Enable Register (IE) Interrupt Priority Register (IP)

  15. Interrupt Vectors

  16. Ex0 ISR using C program • void Ex0Isr(void) interrupt 0 using 1 • { • … • } • Interrupt 0 makes this Ex0’s ISR • Ex0 interrupts vector to 0003 • using 1 • Context switches to bank 1

  17. Interrupt when high priority interrupts a low priority interrupt time Main program EX0 ISR EX1 ISR

  18. Interrupt when low priority interrupts during low priority interrupt time Main program EX0 ISR EX1 ISR

  19. Example using interrupt for INT0 ; ; CIRCUIT ; Vcc ; | ; 8051 |-| ; ---- | | 270R ; | | | Vcc ; | LED |_| | ; | |\ / | |-| ; P3.4 |-|->0---(/)--- | | 100K ; | |/ \// | | ; | Schmitt |_| ; | /| /| | ; P3.2 |-----o<-|----o< |----------|------| ; | \| \| | | ; | | | ; | 0.01uF --- / ; | --- / Switch ; | | o/ ; | | | ; | ---|---- ; | Gnd ; ; ;

  20. ; FLOWCHARTs ; ; A. Main Program ; ; ------------------ ; |Initialise Program| ; | variables | ; ------------------ ; | ; ------------------ ; | Configure INT0 | ; | as edge-sensitive| ; ------------------ ; | ; ------------------ ; | Enable INT0 | ; | interrupt | ; ------------------ ; |---------<------ ; ------------------ | ; | Toggle LED | | ; ------------------ | ; | | ; ------------------ | ; | Call delay | | ; ------------------ | ; | | ; ---------->------ ; ; ;------------------------------------------------------------- ; ; B. External Interrupt0 ISR ; ; ------------------ ; | Alternate | ; | Flash Type (S,F) | ; ------------------ ; | ; ------------------- ; |Update Flash Rate | ; |based on Flash Type| ; ------------------- ;

  21. ;********************************************************************;******************************************************************** PORT_PIN_LED EQU P3.4 ; Connected to red LED on evaluation ; board FLASH_RATE EQU 70H ; Address of location that controls the ; length of the delay SLOW_FLASH EQU 0FFH ; Constant value for creating slow flash rate FAST_FLASH EQU 06FH ; Constant value for creating fast flash rate FLASH_TYPE EQU 7FH ; Bit address for flag to indicate flash type ; 0 Slow, 1 Fast ;____________________________________________________________________ ; MAIN PROGRAM CSEG ORG 0000H LJMP main ORG 0003H ; Code for ISR for INT0 ; Note that IE0 is automatically cleared MOV FLASH_RATE,#SLOW_FLASH CPL FLASH_TYPE JNB FLASH_TYPE, lb1 MOV FLASH_RATE,#FAST_FLASH lb1: RETI

  22. ORG 0048H main: ; Start with slow Flash rate CLR FLASH_TYPE MOV FLASH_RATE,#SLOW_FLASH   ; Set up INT0 pin for edge triggered interrupt SETB IT0 ; Bit 0 of TCON (TCON.0) ;Enable Interrupt on INTO port pin SETB EX0 SETB EA loop: CPL PORT_PIN_LED ; flash (complement) the red LED CALL delay JMP loop ;-------------------------------------------------------------- ; Subroutine : delay ; Description : Subroutine which introduces a time by ; repeatedly executing an instruction ; The repetition is controlled by nested loops. ;oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo delay: MOV R7,FLASH_RATE dly1: MOV R6,#229 dly2: DJNZ R6,dly2 DJNZ R7,dly1 RET ;____________________________________________________________________ END

  23. Appendix

  24. Edge Triggered Interrupts • In the case of an edge triggered interrupt, it is the transition (1 to 0 on 8051) that signals an interrupt. • When the transition occurs, this causes a flag to be set in the CPU. • The edge triggered method is useful if the I/O device generates an interrupt pulse that is short and may be missed if a level triggered interrupt is used. • It may also happen that the I/O device generates a very long interrupt pulse, that remains active even after the ISR is complete. • In this case the edge triggered method will prevent an invalid interrupt occurring after the ISR is complete.

  25. Level Triggered Interrupts • With a level triggered interrupt, the CPU samples the signal on the interrupt input at regular intervals (typically once every machine cycle). • If the signal is active at this time, then a flag is set in the CPU and the interrupt handling process is initiated. • The level triggered interrupt is required when using the wired-OR approach to handle multiple interrupting devices on one CPU interrupt line. • Care must be taken with level triggered interrupts to ensure that the interrupt is cleared, so that the interrupt line on the CPU will not be active after the ISR. • This is not the case with edge triggered interrupts.