SEED-2002 Support of Educational Course for Electronic Design

1. SEED-2002 Support of Educational Course for Electronic Design Dipl.-Inf. Patrick R. Haspel haspel@uni-mannheim.de Computer Architecture Group University of Mannheim, Germany SEED-2002

2. University / Industry Cooperation • Improve quality and curricula of electronic design courses/lectures and practical exercises • Efficient use of EDA tools requires experience students don’t have • Thorough understanding of underlying methodologies is a must for the lecturer • Most universities skip physical design or favor FPGAs • Students are trained on leading-edge and most innovative Cadence EDA tools • Cadence gains: • feedback on usability of EDA tools • students’ learning progress and experiences SEED-2002

3. Participants • ASIC Competence Center (ASICCC)A central point of know-how and experience exchange of researchers and Ph.D. students working on ASIC design • University of Mannheim • Computer Architecture Group (Prof. Brüning) • Circuit Design and Simulation Group (Prof. Fischer) • University of Kaiserslautern • Micro Electronics Group, Prof. Tielert • University of Heidelberg • Computer Engineering Group, Prof. Lindenstruth • Cadence Design SystemsVCAD Services, Feldkirchen, Germany SEED-2002

4. SEED covers the entire design flow • Found new or restructure existing lectures at the participating universities to cover • computer architecture / system architecture • RTL coding, methods for efficient testbench / testpattern generation • high-level synthesis and interface design • synthesis, place and route, extraction, static timing analysis • full custom analog and standard cell design • integration/mergence of both worlds by timing, power and functional characterization as well as abstract generation (.lef). SEED-2002

5. First Results (diploma students) • Founded lecture ‚SemiCustom Design Flow‘ at the University of Mannheim • First students graduated • Covers cell-based design methodology (lecture) and real-world chip designs (practical course) • Two restructured lectures ‚Microelectronic I‘ and ‚VLSI Design‘ (next semester) at the University of Heidelberg • Introduction of FirstEncounter • Founded ‚Design Project Seminar‘ (next semester) at the University of Kaiserslautern • students solve problems given by industrial partners in the area of full custom design • Very positive and encouraging feedback from industry on students´ know how SEED-2002

6. First Results (Ph.D. students) • TRAP2 • taped out May 2003 over IMEC for UMC´s mixed-signal 0.18µ CMOS • 5 x 7,4 mm² die area, 5 custom memory blocks, 167 MHz • 23 low power ADCs, temperature sensor • OASE • 5 x 2,17 mm² die area • 2.5 GHz PLL, serializer and CML I/Os • TRAP2 bonding compatibility to allow chip-to-chip bonding SEED-2002

7. Competence Summary • High performance chip design • HW/SW Codesign and -simulation • tight relations to EDA tool vendors deliver complete tool chain • APU (ATOLL Processing Unit and SW) • Clustercomputing • SAN Architectures • SW for reliable clusters and cluster management • Parallel programming interfaces and libraries SEED-2002