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Panel Discussion High Level Design and ESL: Who Cares?

Panel Discussion High Level Design and ESL: Who Cares?. Masahiro Fujita VLSI Design and Education Center (VDEC) University of Tokyo. Questions from the organizer (1). With HL design models verification becomes easier or harder ? HL models could be golden for RTL verification

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Panel Discussion High Level Design and ESL: Who Cares?

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  1. Panel DiscussionHigh Level Design and ESL: Who Cares? Masahiro Fujita VLSI Design and Education Center (VDEC) University of Tokyo

  2. Questions from the organizer (1) • With HL design models verification becomes easier or harder ? • HL models could be golden for RTL verification • This is, I believe, why industrial people are writing HL models • There are RTL specific properties to be verified, such as clock crossing issues

  3. Questions from the organizer (2) • Starting with HL is good in general ? • Good for more application specific ones, such as SoC • Good for the designs where high level synthesis tools work pretty well, such as DSP type computation • This is, I believe, why industrial people are writing HL models • May not be good for microprocessor designs where performance are critical, and designs themselves are very similar to one another • How about BlueSpec ? It may be useful

  4. Questions from the organizer (3) • Rationale to start with HL (cost effective ?) • Industrial designers (architects) like to have golden model in the beginning to make sure the overall behaviors • Then, how can we use it ? • Also they like to explore more design space with HL models • Need reasonably good high/system-level synthesis tools • For HW/SW co-design, yes • Discuss in the next slides • Equivalence checking may not be so powerful • For speed up of scientific computing, must be • Discuss in the following

  5. High level design flow and verification (Ideal case for HW/SW co-design) • Tools have been actually developed under Japanese Space Agency (JAXA) • JAXA, Toshiba, NEC, Fujitsu, UCI (Prof. Gajski) and U. of Tokyo Algorithmic design description Design optimization Many steps of manual refinement Sequential Equivalence Checking High level synthesizable description Static/ Model checking Design optimization High level synthesis Many steps of manual refinement Register Transfer Level description Design optimization Really used for space satellite designs in Japan

  6. My conclusions • If you can have correct RTL by itself, you do not need HL models • Designing something very similar to previous ones • If you need to develop something very new, starting with RTL designs is very difficutl • Need to explore design space in architectural designs, which need HL models anyway • Need to establish functionally correct HL models as golden for RTL designs • If you are working under HW/SW co-designs, anyway we have HL models • Need good and consistent supports in system-level

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