1 / 11

Nuclear Physics Group Meeting Version-2 Latch Card Testing

This document details the testing protocols and results for the Latch Card Version 2 utilized in nuclear physics. It covers the Control and Status Register (CSR2), trigger/busy functionalities, and signal testing. Key highlights include the internal clock settings at 125 MHz, the adjustable delay parameters, and testing for jittering in the trigger/busy signals. We outline the tested input data patterns, results from FIFO readout, and further testing recommendations based on extensive data collection and operational windows.

yul
Download Presentation

Nuclear Physics Group Meeting Version-2 Latch Card Testing

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Nuclear Physics Group MeetingVersion-2 Latch Card Testing 2011/01/12 Jia-Ye Chen

  2. Content • Latch Card Version 2 • Control and Status Register 2 • Trigger/Busy • Testing Signal • Testing Results • Further Testing

  3. Latch Card Version 2 • Edge Trigger Mode • Internal Clock : 125 MHz (8 ns) • 2nd Control and Status Register • CSR2 (default : 0x000000c0) • FIFO status register = 01 (default = 00) Trigger Busy

  4. Control and Status Register 2 (CSR2) • Adjustable Delay • 64 clocks * 8 ns = 512 ns • Delay=0, earliest signal (default) • Delay=3f, edge signal • 6-clock OR operation window latchORoperation(iOR,iDelay);

  5. Trigger/Busy Trigger Busy Jittering (Two 33MHz Readout Internal Clocks)

  6. Testing Signal signal latch trigger sis3610 trigger latch busy

  7. OR-window and Delay Test (I) • Input Data Pattern (0x ff7f fffefeff 7fff) • 5-event FIFO Readout is exactly identical. • First 6-clock window output as the fine scanning boundary. latchRunTest(id,runs); id : latch card id runs : number of iteration

  8. OR-window and Delay Test (II) Delay Box = 192 ns Delay Box = 128 ns

  9. OR-window and Delay Test (III) Delay Box = 128 ns Scan 100 times Delay Box = 64 ns

  10. CODA Readout (14 hours)

  11. Further Testing • Non-uniform data pattern input testing.

More Related