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CAD Issues & Algorithms(1). Contents. CAD Issues & Algorithms. 1. Simulation 2. Verification 3. Synthesis 4. Place & Route. 1. Simulation 1) Circuit Simulation. Function DC analysis, AC analysis, noise analysis, transient or time-domain analysis very accurate but spends much time

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cad issues algorithms

Contents

CAD Issues & Algorithms

1. Simulation

2. Verification

3. Synthesis

4. Place & Route

1 simulation 1 circuit simulation
1. Simulation1) Circuit Simulation
  • Function
    • DC analysis, AC analysis, noise analysis, transient or time-domain analysis
    • very accurate but spends much time
  • Method
    • treat the circuit as a continuous dynamical system and obtain a set of nonlinear algebraic-differential equations with electrical variables such as voltage, current, and charge to describe its behavior
    • Gaussian elimination : O(N3), N:number of nodes
    • Sparse matrix : O(N1.5), only neighboring nodes have interconnecting elements to reduce analysis time
  • SPICE
    • the very popular circuit simulation tool developed at Berkeley
    • HSPICE - most commercially used
slide4

start

t=t0

Numerical

integration

t=t+t

Newton-Raphson

linearization

Gaussian

elimination

No

t=tstop

Yes

stop

Circuit simulation

algorithm

Nonlinear differential equation

f(x,x’,t) = 0

Nonlinear simultaneous equations

g(x) = 0

Linear simultaneous equations

Ax = b

2 switch level simulation

1

0

X

open switch

closed switch

indeterminate

2) Switch-level Simulation
  • Motivation
    • SPICE simulation is too slow for a large digital system.
    • Logic simulation may give misleading simulation results for systems built from MOS transistors <- bidirectionality of signal flow, charge sharing effects, and transistor sizes.
    • Switch-level simulation is the lowest level of digital simulation.

transistor as a gate-controlled switch

slide6

Network model

Storage node : state is determined by the operation of network

Vdd

Input node : strong signals to the system, ex) Vdd, Gnd, clock, data inputs

out

(4,1)

2

3

gnd

(4,0)

(s)

Edge : transistor

s : strength, or conductance relative to those of TRs in a ratioed circuit

(c, l)

c : node capacitance relative to that of other nodes with which it may share charge, Vdd, Gnd has maximum value

l : logic level, one of (0, 1, X)

Range of c and s

1<=c<=K, for storage nodes

K<s<W, for transistor strength

c = W, for input nodes

slide7

Network partitioning

Gate input is terminated

Each subnetwork is simulated to find steady-state response

slide8

. . . .

root(p)

dest(p)

2 3 5

4 4 6

(4,0)

(3,0)

strength=2

strength=3

1

1

0

0

0

1

3

5

2

3

3

2

(5,1)

maximum strength = 5same input values 1,1,1

4

(4,0)

4

(3,X)

conflicting input values 0,1,1

2

1

0

1

Steady-state response of subnetwork

Strength of conducting path = min(size(root(p)), min(strength of transistors))

Strength and level of storage node

3 logic simulation
3) Logic Simulation
  • Simulation model
    • using logic gate model - AND, OR, NOT, NAND, NOR, Flip-Flop, etc.
    • I/O value representation - Boolean logic value: 0, 1, X(unknown)
    • time - integer, defined by a multiple of unit delay
  • Classification by delay consideration
    • unit-delay simulator
      • assumes that each component has a unit delay
      • avoids modeling any circuit delays

iii) simulates function but not performance

    • variable-delay simulator

i) allow components to have arbitrary delays

ii) allow for more accurate modeling of fast-changing nets

slide10
Delay model
    • model delays physically occurring in logic gates
    • enable accurate performance analysis of the logic designed
    • embedded in logic simulation engines
    • transport delay, ambiguity delay, rise-fall delay, inertial delay

A

B

I=1, T=1

Transport delay

B

I=4

Inertial delay

minimum duration for changing gate state

slide11

t=0

t=1

t=0

t=4,5

X

t=1

Z

t=1

Z

W

t=2

t=2

t=2

Z

Z

t=3

t=3

t=3

Y

W

W

t=3,4

t=4

W

t=4

W

t=4

t=2

t=0

t=1

t=2

t=3

t=4

  • Event-driven simulation
    • evaluate a component only when an even occurs on its input
    • keep track of event on a time wheel, which stores event in time order
    • spin the time wheel forward to the next time slot with an event, and start simulating from there
    • evaluating a component can cause a new event to be added to later slots in the time wheel for later action

Delay

X,W:1

Y,Z:2

slide12
Compiled simulation
    • translate the given logic circuit into a fast code which is compiled and executed

1. Do a levelization - determining evaluation order of gates in the given circuit for correct simulation, a kind of topological sorting

2. Generate code for evaluating each gate from lower level to high level

3. Compile the generated code

4. Run the compiled code

/* level = 1 */

f=b^c;

store P, f

g=d^e;

store Q,g

/* level = 2 */

h=a^f;

store R,h

i=f^g;

store S,i

/* level = 3 */

j=h^i;

store T, j;

4 fault simulation
4) Fault Simulation
  • Digital logic testing
    • defect : physical deviation from some specified properties
    • error : incorrect response to applied stimuli caused by the presence of defects
    • test : an experiment to detect defects and the source of them
  • Fault model
    • models defects introduced during manufacturing
    • stuck-at-0(/1) : the defect causes a logic gate output to be always 0(or 1)
    • Single fault assumption : only one fault at any time in a circuit

This input pattern can detect the fault

1 -->

1 -->

--> 1

--> 0

1 -->

1 -->

Fault-free circuit

Bottom input is s-a-0

slide14

start

Initial fault list

Fault coverage

Generate stimulus to

cover some remaining faults

100%

Fault simulation

Remove faults covered

from fault list

# of test vectors

Coverage OK?

stop

Test pattern generation satisfying target coverage

slide15

Test pattern

Fault

list

11001111

01011111

10101110

Fault injection

Fault-free

circuit

Faulty

circuit

+

Compare

1

0

Fault detection failed

Fault detection

Fault simulation

  • Appications
    • evaluation of a test sequence in terms of its fault detection and location capability
    • analysis of circuit under failure condition
  • Methods
    • general

i) serial

ii) parallel

iii) deductive

iv) concurrent

    • combinational circuits

i) parallel pattern methods

ii) trace-based

iii) combined

    • synchronous sequential circuits

i) modified parallel(PROOFS)

slide16

Fault-free

circuit

+

Test pattern

Circuit

with fault #1

11001111

01011111

10101110

+

Circuit

with fault #2

……..

+

Circuit

with fault #N-1

  • Serial fault simulation
    • iteration of logic simulation after injecting each fault -> heavy simulation time
  • Parallel fault simulation
    • simulating fault-free circuit and N-1 faulty circuits simultaneously
    • N = word size of host machine

A,B,C : 4 bit value

C = A & B performs 4 evaluations in parallel

slide17
Deductive fault simulation
    • simulate a large # of faults in one pass
    • only a few faults may produce values different from fault-free values
    • approach - keep fault-free values and differences

Fault list : a set of faults that complement the fault-free value at a line

After simulation of fault-free circuit, fault list is deductively constructed based on the fault-free logic values on each line

This can detect a/1 --> La={a/1}

This can

i)detect c/1

ii)La because a has controlling value

and

Lb is eliminated because b has non-controlling value

 Lc=(La - Lb) U {c/1}

This can detect b/0 --> Lb={b/0}

slide18

La = {a/1}; Lb = {b/0}; Ld = {d/1};

Le = (La - Lb) U {e/0} = {a/1, e/0},

Lf = (Ld - Lb) U {f/1} = {d/1, f/1}

Lg = (Le - Lf) U {g/0} = {a/1, e/0, g/0}

----> input pattern 010 can detect faults a/1,e/0 and g/0

slide19
Concurrent fault simulation
    • keep a fault list(with I/O values) for each gate
    • when inputs to a gate change or faults are propagated, dynamically update the fault list for the gate

Input pattern abdf=0000 detect faults f/1 and g/0

Input pattern abdf=1001 detect faults

b/1,c/0,e/0,f/0, and g/1

2 verification 1 timing verification
2. Verification1) Timing Verification
  • 주어진 디지털 회로에 대하여 얼마나 빨리 동작할 수 있는 지와 디자인의 어느 부분을 개선해야 하는지에 대한 정보를 얻는 과정.
  • Critical delay (TC)와 critical path
    • Primary output이 최종 값으로 안정화 되는데 걸리는 가장 긴 시간과 해당 패스.
    • TC가 클럭 주기(TCLK) 보다 길지 않아야 회로가 정상 동작한다.

TC <= TCLK

slide22
Topologically longest path
    • 간단히 빠르게 구할 수 있다.
    • 회로의 실제 딜레이는 구해진 값보다 짧을 수 있다 (false path problem).

0

0

10

10

20

20

1

1

Topologically longest path = 40

Actual delay = 30

slide23
타이밍 시뮬레이션 (Dynamic timing analysis)
    • 주어진 입력 벡터를 이용하여 시뮬레이션 하여 크리티컬 딜레이와 패스를 찾는다.
    • 입력 데이터에 따르는 결과만을 출력할 수 있다.
    • 수행시간이 가능한 입력 벡터에 따라 선형적으로 늘어나며 입력벡터는 회로의 복잡도에 따라 기하급수적으로 증가한다.
slide24
Static Timing analysis
    • Best first search에 기반을 두고 있다.

i) Topologically longest path가 false path가 아닌지를 검사한다.

ii) 아니면 sensitizable path로서 critical path가 된다.

iii) False path인 경우 다음으로 긴 패스에 대하여 위의 작업을 반복한다.

    • False path인지를 효과적으로 빠르게 판단하기 위하여 path sensitization criteria를 정의하여 사용한다.

i) Path sensitization criteria는 주어진 패스의 입력에서 패스의 최종 출력까지 신호를 전달하는 입력이 있는지 없는지를 결정하기 위해 사용되는 룰의 집합으로 이것에 의해 Timing analysis의 정확도가 결정된다.

ii) 연산속도와 정확도의 트래이드 오프를 위하여 수 많은 path sensitization criteria가 제안되어 왔다.

2 functional verification
2) Functional Verification
  • 정의
    • 실제로 구현한 system이 주어진 functional spec.을 만족하는지 확인하는 작업
  • Complete verification 방법
    • Implicit enumeration method
    • BDD-based method
    • Formal method
  • Equivalence checking, correctness checking

Specification

Golden

Reference

Model

(Ideal model)

Design

Equivalence

Correctness

slide26

s0

s2

q0

q2

s1

  • Implicit Enumeration-State machine
    • 목표

i) 주어진 두개의 state machine에서 같은 input sequence에 대해 같은 output sequence를 내는 state pair를 찾는다.

    • 방법

i) State machine S, Q 중 si는 S의 state, qi는 Q의 state

ii) si와 qi가 같은 입력에 같은 출력을 내는지 확인하고, 같은 출력을 낸다면 같은 입력에 대한 next state도 마찬가지인지 계속해서 확인한다.

s0  q0

i2

i1

i3/o3

s2  q1

s1  q0

i2/o2

i1/o1

i3/o3

i2

i1

i1/o1

i1/o1

s0  q0

s2  q1

i2/o2

i2/o2

i3

s0  q0

slide27
BDD(Binary Decision Diagram)
    • 구성

i) Internal node: Variable을 나타냄

ii) Leaf node: 0, 1 두 가지가 있으며 function의 값을 나타냄

iii) Edge: Variable이 0 일 때, 1 일 때의 상황을 나타냄

iv) 0 edge와 1 edge가 같은 internal node는 없앤다.

    • 특징

i) Variable 순서가 같으면 functionality에 따라 유일한 모양을 가진다.

ii) BDD 상호간의 operation은 다음과 같은 recursive equation으로 정의된다.

slide28

x1

  • BDD 예제
  • Combinational network의 equivalence check
    • 두 network에 대해 같은 variable 순으로 BDD를 만들고 reduction 한다. (ROBDD)
    • 두 BDD가 isomorphic 하면 equivalent 하다.

1

0

x2

F= x1*x2 + x3

0

x3

1

1

0

0

1

slide29
Formal verification
    • Design과 specification을 모두 엄격한 수학적 논리에 바탕을 둔 “language”로 기술을 하고, symbolic manipulation을 이용하여 검증하는 방법
    • Higher-order logic 혹은 temporal logic 등으로 spec과 design을 표현하고 theorem prover를 이용, logic을 확인하는 방법이 주로 쓰인다.
  • Temporal logic
    • 기존의 predicate logic에 시간적인 개념을 도입하여 일반화 시킴
    • Finite state system은 state transition graph로 표현가능하며, 이는 temporal logic으로 formulation이 가능하다.
slide30

R

unwind

R

R

G

G

R

Y

G

Y

G

Y

R

  • Computational Tree Logic (CTL)
    • State transition graph를 풀면 initial state를 root로 한 infinite tree가 생겨남. 이 tree의 path는 system의 모든 가능한 state와 그 state에 도달하는 과정을 나타낸다.
slide31
CTL의 구성
    • Path quantifier (A, E)

i) A: 모든 경로를 나타냄 (모든 도달 가능한 state …)

ii) E: 어떤 경로를 나타냄 (어떤 도달 가능한 state …)

    • Temporal modality(F, G, X, U)

i) F  :  가 현재 state이후 언젠가 참이 되면 참이다.

ii) G  :  가 현재 state이후 항상 참이면 참이다.

iii) X  :  가 현재 state의 바로 다음 state에서 참이면 참이다.

iv)  U  :  가 현재 state 이후 언젠가 참이 되고, 그 이전 state에서  가 항상 참이면 참이다.

slide32
Traffic light controller specification
    • hwy_light 와 farm_light는 동시에 green이 되서는 안된다.

i) farm_light와 hwy_light가 동시에 green인 상태는 모든 경로에, 항상 거짓이여야 한다.

ii) AG ( !((farm_light =green) * (hwy_light=green)))

    • farm road가 어떤 상태였던 간에 hwy_light는 언젠가 green이 되어야 한다.

i) 모든 경로에 대해 언젠가 hwy_light가 green이 되는 경우는 모든 경로에 대해 항상 참이여야 한다.

ii) AG(AF(hwy_light=green))