Lecture 20

1. Lecture 20 Today we will • Look at why our NMOS and PMOS inverters might not be the best inverter designs • Introduce the CMOS inverter • Analyze how the CMOS inverter works

2. NMOS Inverter 5 V 5 V When VIN is logic 1, VOUT is logic 0. Constant nonzero current flows through transistor. Power is used even though no new computation is being performed. When VIN changes to logic 0, transistor gets cutoff. ID goes to 0. Resistor voltage goes to zero. VOUT “pulled up” to 5 V. R R VOUT D ID = 5/R VOUT D ID = 0 VIN 0 V VIN 5 V + VDS _ + VDS _ 5 V 0 V

3. PMOS Inverter 5 V 5 V When VIN is logic 0, VOUT is logic 1. Constant nonzero current flows through transistor. Power is used even though no new computation is being performed. When VIN changes to logic 1, transistor gets cutoff. ID goes to 0. Resistor voltage goes to zero. VOUT “pulled down” to 0 V. VIN VIN - VDS + - VDS + VOUT VOUT 0 V 5 V ID = -5/R 5 V ID = 0 0 V R R

4. Analysis of CMOS Inverter VDD (Logic 1) • We can follow the same procedure to solve for currents and voltages in the CMOS inverter as we did for the single NMOS and PMOS circuits. • Remember, now we have two transistors so we write two I-V relationships and have twice the number of variables. • We can roughly analyze the CMOS inverter graphically. S VOUT D D VIN S NMOS is “pull-down device” PMOS is “pull-up device” Each shuts off when not pulling

5. NMOS Inverter ID VGS = 3 V X Linear ID vs VDS given by surrounding circuit VGS = 1 V X VDS

6. Linear KVL and KCL Equations VDD (Logic 1) VGS(n) = VIN VGS(p) = VIN – VDD VGS(p) = VDS(n) - VDD ID(p) = -ID(n) VDS(n) = VOUT VDS(p) = VOUT – VDD VDS(p) = VDS(n) - VDD + VGS(p) - S VOUT D + VDS(n) _ D VIN + VGS(n) - S Use these equations to write both I-V equations in terms of VDS(n) and ID(n)

7. CMOS Analysis ID(n) As VIN goes up, VGS(n) gets bigger and VGS(p) gets less negative. NMOS I-V curve PMOS I-V curve (written in terms of NMOS variables) VIN = VGS(n) = 0.9 V VDS(n) VDD

8. CMOS Analysis ID(n) As VIN goes up, VGS(n) gets bigger and VGS(p) gets less negative. NMOS I-V curve PMOS I-V curve (written in terms of NMOS variables) VIN = VGS(n) = 1.5 V VDS(n) VDD

9. CMOS Analysis ID(n) As VIN goes up, VGS(n) gets bigger and VGS(p) gets less negative. NMOS I-V curve PMOS I-V curve (written in terms of NMOS variables) VIN = VGS(n) = 2.0 V VDS(n) VDD

10. CMOS Analysis ID(n) As VIN goes up, VGS(n) gets bigger and VGS(p) gets less negative. NMOS I-V curve PMOS I-V curve (written in terms of NMOS variables) VIN = VGS(n) = 2.5 V VDS(n) VDD

11. CMOS Analysis ID(n) As VIN goes up, VGS(n) gets bigger and VGS(p) gets less negative. NMOS I-V curve PMOS I-V curve (written in terms of NMOS variables) VIN = VGS(n) = 3.0 V VDS(n) VDD

12. CMOS Analysis ID(n) As VIN goes up, VGS(n) gets bigger and VGS(p) gets less negative. NMOS I-V curve PMOS I-V curve (written in terms of NMOS variables) VIN = VGS(n) = 3.5 V VDS(n) VDD

13. CMOS Analysis ID(n) As VIN goes up, VGS(n) gets bigger and VGS(p) gets less negative. NMOS I-V curve PMOS I-V curve (written in terms of NMOS variables) VIN = VGS(n) = 4.1 V VDS(n) VDD

14. CMOS Inverter VOUT vs. VIN VOUT both sat. curve very steep here; only in “C” for small interval of VIN VDD NMOS: cutoff PMOS: triode NMOS: triode PMOS: cutoff NMOS: triode PMOS: saturation NMOS: saturation PMOS: triode VIN D E B C A VDD

15. CMOS Inverter ID ID VIN D E B C A VDD

16. VDD S VOUT1 VDD D S D VOUT2 D D S S Important Points • No ID current flow in Regions A and E if nothing attached to output; current flows only during logic transition • If another inverter (or other CMOS logic) attached to output, transistor gate terminals of attached stage do not permit current: current still flows only during logic transition VIN