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Since February - PowerPoint PPT Presentation


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Since February. Clock Driver Needed Improvement. Original Version. ADC Clock outputs slow due to level shifter. Level Shifter. Buffer. Improved Version. V EE Routing Optimization. V EE ~ 5 mV. DELAY. GAIN BITS PIPELINE +OUTPUT. CLOCK I/O. V EED pad. COMMAND DECODER.

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Presentation Transcript
original version
Original Version

ADC Clock outputs slow

due to level shifter

Level Shifter

Buffer

v ee routing optimization
VEE Routing Optimization

VEE ~ 5 mV

DELAY

GAIN BITS

PIPELINE

+OUTPUT

CLOCK I/O

VEED

pad

COMMAND DECODER

digital bias distribution
Digital Bias Distribution

I

I’

VBIAS~0

VEE

VEE’

timing
Timing

Fixed

Delay

S/H

(Internal clocks)

CKi

Variable

Delay

CKAD

(to ADC)

Input clock (CKi) is the “observable”

All subsequent timings relative to CKi

t h timing
T/H Timing

CK H = 8.5 ns

CKi

S/H

FPUout

timing relations
Timing Relations

N+1

N+2

N+3

N+4

N

Signal

CKi

S

S/H

H

CKAD

N-3

N-2

N-1

N

ADC

N-3

N-2

N-1

N

FPUo

fpu output bit timing
FPU Output Bit Timing

CK FPo = 14.2 ns

S/H FPo = 5.7 ns

2.5 pipeline delays

timing diagram
Timing Diagram

N

Signal

CKi

S

S/H

H

8.5 ns

CKAD

8.9 ns

9 typ ns

N-3

N-2

ADC

N-3

N-2

FPUo

14.2 ns