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Consistent Placement of Macro-Blocks Using Floorplanning and Standard-Cell Placement

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  1. Consistent Placement of Macro-Blocks Using Floorplanning and Standard-Cell Placement Saurabh Adya Igor Markov (University of Michigan)

  2. Outline • Motivations for mixed-mode placement • Previous Work • Components of our flow • Fixed-outline floorplanning • Standard-Cell placement • Mixed-mode placement flow • New Benchmarks • Results • Conclusions

  3. Motivation • IP reuse : PD with large rectangular blocks • Integrated partitioning, FP & placement • Older flows apply separate optimizations • New generation of fast (min-cut) placers enable an integrated approach • Partitioner is part of the placer • Shifted cutlines perform floorplanning • However handling large macros by RB is difficult • Small macros can be handled by RB (not in our work) • Capo, Dragon, Feng Shui, etc. • can’t place large macros w/o overlaps

  4. Previous Work • Continuous optimization techniques • Force directed approaches • [Eisenmann, Johannes, DAC ‘98] : mixed-mode • [Mo et. al, ICCAD ‘00] : macros only + congestion • Are good with a lot of white-space in design • Otherwise, designer must remove overlaps • Combinatorial optimization techniques • Particularly promising on constrained designs • [Nag et. al, DATE ‘98]: macros only • This work: mixed-mode

  5. Cadence-recommended Mixed-Mode Flow for SEDSM • SEDSM places blocks at the periphery • Designer manually removes overlaps • From now on, blocks are considered fixed • QPlace is called to place standard-cells • Otherwise, as our experiments show, • Handling many large cells is not ideal in QPlace • Next-gen Cadence mixed-mode layout tool • In -testing • Preliminary results are good

  6. SEDSM Output (not new gen!)

  7. Our Proposed Flow (Outline) • Generate initial placement using an arbitrary, min-WL standard-cell placer • Generate a fixed-outline floorplanning instance by “physical clustering” • Remove overlaps and generate valid macro locations using a fixed-outline floorplanner • Place small cells using standard-cell placer with macros considered fixed • (details – later)

  8. Component : 1 • Fast min-cut std-cell placer (Capo) • [Caldwell, Kahng and Markov, DAC 2000] • Algorithms used • Min-cut bisection, optimal end-case placers • Multi-level FM partitioning • Cut-lines allowed to move, adaptive part. toler. • Yet, Capo does not handle large macros So on

  9. Component : 2 • Fixed-outline floorplanner (Parquet) • [Adya and Markov, ICCD 2001] • Solves a constraint satisfaction problemwhile minimizing wirelength • Uses enhanced local search during annealingto satisfy outline constraints   x-span y-span

  10. Floorplan “Slack” • Slack for block A in x- or y- dimension • The distance that A can be moved in x- or y- dimension without increasing the x- or y- span • “Critical” blocks have zero slack • Critical blocks lie on critical paths: analogy w STA • We want to move critical blocks to improve fplan F D F D critical blocks E E C C B B x-slack for block A = x(Aright) – x(Aleft) A A Left Packing Right Packing

  11. Fixed-outline FP’er Parquet(based on Simulated Annealing) Restart  current outline S.A. y-violation S.A. S.A.  x-violation required outline

  12. In This Work: Improvements to Parquet • HPWL minimization • Local annealing objective = linear combination of area and wirelength • Additional moves designed to improve HPWL • Handling soft blocks • X/Y slacks suggest changes to AR of a block • At regular intervals during annealing • Sort blocks according to slacks • Shape blocks as suggested by the slacks • Try to greedily reshape every soft blocks

  13. Mixed-mode Placement Flow (1) • Find a tentative placement of macros • Shred macros into fake standard-cells • Connect sub-cells with fake wires (pics follow) • Place “shredded netlist’’ using Capo • Compute locs of macros as average locs of sub-cells • (continued later)

  14. Shredding Macro Cells • Shred all macros into smaller sub-cells • Determine location of macros by averaging locations of sub-cells • Determine the prevailing orientation of each macro (Should work with many min-WL placers) Va Case: Orient Va Vr : N Va Vr : S Va Vr : W Va Vr : E …etc(4 more cases) End Case; 3 Macro Vr 2 1 0 0 1 2

  15. Shredding Macro Cells (cont) • Some macros may have fixed orientation • We tie the corner sub-cells to the corners of layout • (fake wires tying shredded pieces must be stronger) • Lemma: this works for min-HPWL placers • This does not work for quadratic placers (!) Orient = N Orient = N Orient = W

  16. Initial Placement

  17. Mixed-mode Placement Flow (2) • Find a tentative placement of macros • Shred macros into fake standard-cells • Connect sub-cells with fake wires • Place “shredded netlist’’ using Capo • Compute locs of macros as average locs of sub-cells • Generate a FP instance with soft & hard blocks • Cluster neighboring standard cells into soft blocks • (continued later)

  18. Physical Clustering

  19. Mixed-mode Placement Flow (3) • Find a tentative placement of macros • Shred macros into fake standard-cells • Connect sub-cells with fake wires • Place “shredded netlist’’ using Capo • Compute locs of macros as average locs of sub-cells • Generate a FP instance with soft & hard blocks • Cluster neighboring standard cells into soft blocks • Remove overlaps by fixed-outline floorplanning (Parquet) • (continued later)

  20. Floorplanned Design

  21. Mixed-mode Placement Flow • Find a tentative placement of macros • Shred macros into fake standard-cells • Place “shredded netlist’’ using Capo • Connect sub-cells with fake wires • Compute locs of macros as average locs of sub-cells • Generate a FP instance with soft & hard blocks • Cluster neighboring standard cells into soft blocks • Remove overlaps by fixed-outline FP (Parquet) • Place std. cells consistently with the macros • Fix macros at current locations • Replace all standard cells using Capo

  22. Final Placement

  23. New Benchmarks • Derived from ISPD-98 (IBM) circuits • Original specs give cell areas, but not dimensions • We assumed rowheight = 16 for standard cells • Large cells  macros with AR=1 (cf. Dragon BMs) • Whitespace for each design is 15 % • Fixed pads placed randomly (cf. Dragon BMs) • Available at : • http://vlsicad.eecs.umich.edu/BK/ISPD02benchand through http://www.gigascale.org/bookshelf

  24. Conclusions • Mixed-mode placement increasingly important • Our flow combines techniques fromstd-cell placement & fixed-outline floorplanning • Results: commercial tools can be improved • Source code publicly available through: • http://www.vlsicad.eecs.umich.edu/BK/ • http://www.gigascale.org/bookshelf • Ongoing work • Congestion analysis • Multilevel hierarchical floorplanning

  25. Acknowledgements • Financial support from • Gigascale Silicon Research Center • IBM • Technical support from