F28PL1 Programming Languages

1. F28PL1 Programming Languages Lecture 2: Assembly Language 1

2. CISC & RISC • CISC: complex instruction set computer • original CPUs very simple • poorly suited to evolving high level languages • extended with new instructions • e.g. function calls, non-linear data structures, array bound checking, string manipulation • implemented in microcode • sub-machine code for configuring CPU sub-components • 1 machine code == > 1 microcode • e.g. Intel X86 architecture

3. CISC & RISC • CISC introduced integrated combinations of features • e.g. multiple address modes, conditional execution • required additional circuitry/power • multiple memory cycles per instruction • over elaborate/engineered • many feature combinations not often used in practise • could lead to loss of performance • better to use combinations of simple instructions

4. CISC & RISC • RISC: reduced instruction set computer • return to simpler design • general purpose instructions with small number of common features • less circuitry/power • execute in single cycle • code size grew • performance improved • e.g. ARM, MIPS

5. ARM • Advanced RISC Machines • UK company • originally Acorn • made best selling BBC Microcomputer in 1980s • world leading niche processors • 2009: 90% of all embedded processors • mobile phones, media players, games, peripherals etc • e.g. Nokia, iPod, iPad, Blackberry, Nintendo

6. ARM • 32 bit RISC processor architecture family • many variants • general reference in library: • W. Hohl, ARM Assembly Language, CRC Press, 2009 • ARM7TDMI • ARM does not make chips • licences the IP core (intellectual property) logic design to chip manufacturers

7. Cortex-M3 • ARM CPU in STM32-Discovery board • Thumb2 instruction set • based on ARMV7 • subset of full ARM instructions • 16 bit length instructions • Cortex-M3 manual • http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf

8. MDK-ARM • ARM development environment for: • C & assembler • many ARM-based systems • includes simulator • free restricted download via: • http://www.keil.com/arm/mdkbasic.asp • MDK-ARM/Cortex-M3 guide • http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/USER_MANUAL/CD00283786.pdf

9. Cortex-M3 memory map 0xFFFFFFFF Vendor Specific • linear 4GB address space • modified Harvard architecture in CPU 0xE0100000 External Peripheral Bus 0.5GB 0xE0040000 Internal Peripheral Bus 0xE0000000 External Device 1GB 0xA0000000 External RAM 1GB 0x60000000 Peripheral 0.5GB 0x40000000 SRAM 0.5GB 0x20000000 Code 0.5GB 0x00000000

10. Memory • linear addressing • 2 descending stacks • main stack • process stack – used by OS • all operations based on registers • must move data between registers & memory

11. Registers • 16 * 32 bit registers • working registers • R0-R7 – low registers • R8-R12 – high registers • R13 – stack pointer (SP) • R14 - link register (LR) • R15 – program counter (PC) • PSR – program status register • bits for negative (N), zero (Z), carry (C), overflow (V)

12. Data formats • word • 32 bits • long • half word • 16 bits • int • byte • 8 bits • char

13. Programming approach • in high level programming: • identify variables & types • compiler maps these to memory & data representation • use of memory v registers invisible • in low level programming • must make explicit use of memory & registers • must choose data representation • registers much faster than memory • try to map variables to registers • what if more variables than registers...?

14. Example: sum of 1st 10 integers • we write: #define MAX 11 int s; int n; n = 0; while(n<MAX) { s = s+n; n = n+1; } • C compiler generates: MOVS r2,#0x00 MOVS r1,#0x00 B TEST LOOP ADD r2,r2,r1 ADDS r1,r1,#1 TEST CMP r1,#0x0A BLT LOOP

15. Example: sum of 1st 10 integers • we write: #define MAX 11 int s; int n; n = 0; while(n<MAX) { s = s+n; n = n+1; } • C compiler generates: MOVS r2,#0x00 MOVS r1,#0x00 B TEST LOOP ADD r2,r2,r1 ADDS r1,r1,#1 TEST CMP r1,#0x0A BLT LOOP

16. Example: sum of first 10 integers • s == r2 - register 2 • n == r1 – register 1 MOVS r2,#0x00 • move hexadecimal constant 0x00 to register 2 • set condition code flags MOVS r1,#0x00 • move hexadecimal constant 0x00 to register 2 • set condition code flags B TEST • branch to label TEST

17. Example: sum of first 10 integers LOOP ADD r2,r2,r1 • label LOOP • put in r2 sum of r2 and r1 ADDS r1,r1,#1 • put in r1 sum of r1 and decimal constant #1 • set condition code flags

18. Example: sum of first 10 integers TEST CMP r1,#0x0A • label TEST • compare r1 and hexadecimal constant #0x0A == 10 • set condition code flags BLT LOOP • branch to label LOOP if flags indicate “less than”

19. Instruction format mnemonicoperands • general format • operands depend on instruction mnemonic • meaningful short form • reminds us what instruction does • ARM uses {...} for options • Rd or Rm== register -r0..r15

20. Operands • first operand usually rd • Operand2 == flexible 2nd operand • constant • Rm • constant == 8 hexadecimal digits • constant == decimal • size of decimal depends on instruction • #imm16 == 0-65535 == 16 bit

21. MOV: move MOV Rd, Operand2  Rd= Operand2 • don’t update condition code flags MOVS Rd, Operand2 • as MOV but update condition code flags MOV Rd, #imm16  Rd = imm16

22. ADD: addition ADDRd, Rn, Operand2 Rd= Rn+Operand2 ADDRn, Operand2 Rn= Rn+Operand2 ADDC • add with carry • like ADD+ carry flag ADDS/ADDCS • like ADD/ADDC but set condition code flags

23. SUB: subtraction SUBRd, Rn, Operand2 Rd= Rn-Operand2 SUBRn, Operand2 Rn= Rn-Operand2 SUBC • subtract with carry • like SUB-1 if carry flag not set SUBS/SUBCS • like SUB/SUBC but set condition code flags

24. CMP: compare CMPRn, Operand2 • subtract Operand2 fromRnBUT ... • ... do not modify Rn • otherwise same as SUBS • update Z, N, C, V flags CMN RN, Operand2 • add Operand2 toRnBUT ... • ... do not modify Rn • otherwise same as ADDS • update Z, N, C, V flags

25. Flags • N – 1 if result <0; 0 otherwise • Z – 1 if result =0; 0 otherwise • C – 1 if result led to carry; 0 otherwise • i.e. X+Y > 232 • i.e. X-Y >= 0

26. Flags • V – 1 if result led to overflow; 0 otherwise • (-) == negative • (+) == positive • i.e. (-)X+(-)Y > 0 • i.e. (+)X+(+)Y < 0 • i.e. (-)X-(+)Y > 0 • i.e. (+X)-(-Y) < 0

27. B: branch Blabel • branch to label • i.e. reset PC to address for label Bcondlabel • branch on condition to label

28. condition

29. condition

30. Label • identifier • can precede any line of assembler • represents the address of: • instruction • literal data • relative to program counter (PC) • turned into PC + offset in machine code

31. NOP: no operation NOP • do nothing • use for padding/layout • no cost

32. Layout • ARM assembly language is layout sensitive • must precede instruction with a tab • for labelled instruction, use tab immediately after label • can’t use equivalent number of spaces

33. Example: multiply by adding • m == x*y int x; int y; int m; x = 8; y = 10; m = 0; while(y!=0) { m = m+x; y = y-1; } • x == R1; y == R2; m == R3 MOV R1,#0x08 MOV R2,#0x0A MOV R3,#0x00 LOOP CMP R2,#0x00 BEQ DONE ADD R3,R1 SUB R2,#0x01 B LOOP DONE NOP

34. Register name definition name RN expression • expression  0..15 • name renames the register e.g. x RN 1 y RN 2 m RN 3 MOV x,#0x08 MOV y,#0x0A MOV m,#0x00 LOOP CMP y,#0x00 BEQ DONE ADD m,x SUB y,#0x01 B LOOP DONE NOP

35. Constant name definition nameEQUexpression • name is replace with value from expression e.g. x RN 1 y RN 2 m RN 3 xinit EQU 8 yinit EQU 10 MOV x,#xinit MOV y,#yinit MOV m,#0x00 LOOP CMP y,#0x00 BEQ DONE ADD m,x SUB y,#0x01 B LOOP DONE NOP