Performance of the Cluster Processor Modules Testing. Test Rigs Real Time Data results 160 Mhz 40 Mhz Temperature effect Readout testing Test beam results Latency measurement Production Test Plan. CPM Final Design Review, Birmingham, 22 nd March 2005. Cluster Processor Module: Test.
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CPM Final Design Review, Birmingham,
22nd March 2005
Cluster Processor Module: Testing Process
Unit Under Test
Each individual serialiser show a transition less than 2 ns
Spread of tracks length expand it up to 5 ns
Bit Error Rate Test performed at the input of the serialiser chip: < 10-13 per channel with pseudo random data (modified Serialiser F/W used)
2nd CPM on Left
2nd CPM on Right
RoIs found by the CP are stored in a FIFO and sent to a ROD with a Bunch Crossing Number (BCN) attached on each L1A
DAQ monitoring data, consisting of energies from 80 TT as well as resulting hit multiplicities are also sent to a ROD on each L1A. Data from up to 5 consecutive bunch crossings can be sent