Part Three-- Storage Management

1. Part Three-- Storage Management • Chapter 9Memory Management • Chapter 10VirtualMemory • Chapter 11File-System Interface • Chapter 12File-SystemImplementation

2. Chapter 9: Memory Management

3. Chapter 9: Main Memory • 9.1 Background • 9.2 Swapping • 9.3 Contiguous Memory Allocation • 9.4 Paging • 9.5 Segmentation

4. 9.1 Background • Program must be brought into memory and placed within a process for it to be run. • Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program. • User programs go through several stepsbefore being run.

5. Addresses may be represented in different ways during these steps. • Addresses in the source program are generally symbolic(such as count). • A compiler will typically bind these symbolic addresses to relocatableaddresses (such as "14 bytes from the beginning of this module"). • The linkage editor or loader will in turn bind these relocatab1e addresses to absoluteaddresses (such as 74014). Each binding is a mapping from one address space to another.

6. ◆1. Address Binding Address binding of instructions and data to memory addresses can happen at three different stages. • Compile time • If memory location known a priori, absolute code can be generated; must recompile code if starting location changes. • Load time • Must generate relocatable code if memory location is not known at compile time. • Execution time • Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers).

7. Multistep Processing of a User Program <

8. ◆ 2.Logical vs. Physical Address Space • Logical & Physical Address • logicaladdress • An address generated by the CPU • physicaladdress • an address seen by the memory unit--that is, the one loaded into the memory-address register of the memory

9. virtualaddress • The compile-time and load-time address-binding methods generate identical logical and physical addresses. • However, the execution-time address-binding scheme results in differing logical and physical addresses. In this case, we usually refer to the logical address as a virtualaddress.

10. Logical & Physical Address space • Logical-addressspace • The set of all logical addresses generated by a program; • physical-addressspace • the set of all physical addresses corresponding to these logical addresses. • Thus, in the execution-time address-binding scheme, the logical- and physical-address spaces differ.

11. The concept of a logical address space that is bound to a separate physicaladdress space is central to proper memory management. • Logicaladdress – generated by the CPU; also referred to as virtual address. • Physicaladdress – address seen by the memory unit.

12. Memory-Management Unit (MMU) • Hardware device that maps virtual to physical address. • In MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory. • The user program deals with logical addresses; it never sees the real physical addresses.

13. Dynamic relocation using a relocation register

14. ◆ 3.Dynamic Loading • Routine is not loaded until it is called • Better memory-space utilization; unused routine is never loaded. • Useful when large amounts of code are needed to handle infrequently occurring cases. • No special support from the operating system is required implemented through program design.

15. ◆ 4. Dynamic Linking • staticlinking • system language libraries are treated like any other object module and are combined by the loader into the binary program image.

16. dynamiclinking • Linking postponed until execution time. • This feature is usually used with system libraries, such as language subroutine libraries. • Without this facility all programs on a system need to have a copy of their language library (or at least the routines referenced by the program) included in the executable image. • This requirement wastes both disk space and main memory.

17. stub • Small piece of code, used to locate the appropriate memory-resident library routine. • Stub replaces itself with the address of the routine, and executes the routine. • Dynamic linking is particularly useful for libraries. • support from the operating system is required

18. 9.2 Swapping • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. • Backingstore • fast disk large enough to accommodate copies of all memory images for all users; • must provide direct access to these memory images.

19. Rollout, rollin • swapping variant used for priority-based scheduling algorithms; • lower-priority process is swapped out so higher-priority process can be loaded and executed. • Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. • Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

20. Operating system process P1 ①swap out process P2 ②swap in User space Backing store Figure Swapping of two processes using a disk as a backing store. <

21. 9.3 Contiguous Memory Allocation • Main memory usually into two partitions • Resident operating system • usually held in low memory with interrupt vector. • User processes • held in high memory.

22. Single-partition allocation

23. Relocation-register scheme • used to protect user processes from each other, and from changing operating-system code and data. • Relocation register • contains value of smallest physical address; • limit register • contains range of logical addresses – each logical address must be less than the limit register.

24. memory limit register Relocation register logical address physical address yes CPU < + 14346 no trap; addressing error Figure Hardware support for relocation and limit registers.

25. OS OS OS OS process 5 process 5 process 5 process 5 process 9 process 9 process 8 process 10 process 2 process 2 process 2 process 2 • Multiple-partition allocation • Hole – block of available memory; holes of various size are scattered throughout memory. • When a process arrives, it is allocated memory from a hole large enough to accommodate it. • Operating system maintains information about:a) allocated partitions b) free partitions (hole)

26. Dynamic Storage-Allocation Problem • How to satisfy a request of size n from a list of free holes • First-fit • Allocate the first hole that is big enough. • Best-fit • Allocate the smallest hole that is big enough; • must search entire list, unless ordered by size. • Produces the smallest leftover hole. • Worst-fit • Allocate the largest hole; • must also search entire list. • Produces the largest leftover hole. • First-fit and best-fit better than worst-fit in terms of speed and storage utilization.

27. Fragmentation • ExternalFragmentation • – total memory space exists to satisfy a request, but it is not contiguous. • InternalFragmentation • – allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used.

28. Fragmentation • Reduce external fragmentation by compaction • Shuffle memory contents to place all free memory together in one large block. • Compaction is possible only if relocation is dynamic, and is done at execution time.

29. 9.4 Paging 分页 1. Basic Method • Physical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available. • Frame帧 • Divide physical memory into fixed-sized blocks called frames • size is power of 2, between 512 bytes and 8192 bytes • Page页 • Divide logical memory into blocks of same size called pages.

30. Keep track of all free frames; To run a program of size n pages, need to find n free frames and load program. • pagetable页表 • Set up a page table to translate logical to physical addresses. • Internal fragmentation内碎片

31. the displacement within the page page number page offset an index into the page table p d m-n n Address Translation Scheme地址转换方案 • Address generated by CPU is divided into: • Pagenumber(p) 页号 • – used as an index into a pagetable which contains base address of each page in physical memory. • Page offset (d) 页内偏移量 • – combined with base address to define the physical memory address that is sent to the memory unit.

32. } f logical address physical address f0000…0000 CPU p d f d { f1111…1111 p f Physical memory page table Figure Address Translation Architecture

33. frame number page 0 0 page 1 1 page 0 1 0 2 3 4 1 7 3 page 2 2 page 3 3 page 2 4 page 1 Page table logical memory 5 6 7 page 3 physical memory Figure Paging Example

34. a b c d e f g h i j k l m n o p e f g h a b c d i j k l m n o p 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 4 8 12 0 24 20 16 28 2 3 0 1 1 6 2 5 Example Page table logical memory physical Memory Figure Paging example for a 32-byte memory with 4-byte pages.

35. 13 14 0 1 2 3 14 13 18 20 15 page 0 page 1 page 2 page 3 page 0 page 1 page 2 page 3 16 17 18 new process new process 19 20 21 free-frame list 14 13 18 20 15 free-frame list 15 13 14 15 16 17 18 19 20 21 (a) New-process page table b) Figure Free frames. (a) Before allocation. (b) After allocation.

36. 2. Implementation of Page Table页表的实现 • Page table is kept in main memory. • Page-table base register (PTBR)页表基址寄存器 • points to the page table. • Page-table length register (PTLR)页表长度寄存器 • indicates size of the page table.

37. Every data/instruction access requires two memory accesses. • One for the page table • one for the data/instruction. • The two memory access problem can be solved by the use of a special fast-lookup hardware cache • called associativememory or translationlook-asidebuffers(TLBs) 联想存储器或旁视转换缓冲区

38. Associative Memory (TLBs)联想存储器（寄存器） • Associative memory – parallel search • Address translation (A´, A´´) • If A´ is in associative register, get frame # out. • Otherwise get frame # from page table in memory Page # Frame #

39. Paging Hardware With TLB

40. Effective Access Time有效访问时间 • hit ratio命中率 • The percentage of times that a particular page number is found in the TLB

41. effective access time有效访问时间 • Suppose that, it takes 20 nanoseconds to search the TLB, and 100 nanoseconds to access memory. An 80-percent hit ratio means: • effective access time = 0.80 X 120 + 0.20 X 220 = 140 nanoseconds. • we suffer a 40-percent slowdown in memory access time---from100 to 140 nanoseconds. • For a 98-percent hit ratio, we have • effective access time = 0.98 x 120 + 0.02 x 220 = 122 nanoseconds.

42. 3.Memory Protection存储保护 • Protection Bits保护位 • Protection bits are associated with each frame. • Normally these bits are kept in the page table. • These bits can define a page to be read-write ,read-only , execute-only, and so on. • Every reference to memory goes through the page table to find the correct frame number. • At the same time that the physical address is being computed, the protection bits can be checked to verify that no illegal attempts are being made. • illegal attempts will be trapped to the operating system.

43. Valid-invalid bit有效（无效）位 attached to each entry in the page table: • “valid” • indicates that the associated page is in the process’ logical address space, and is thus a legal page. 指示相应的页在该进程的逻辑地址空间中，因而是合法页。 • “invalid” • indicates that the page is not in the process’ logical address space. • Illegal addresses are trapped by using the valid-invalid bit. • The operating system sets this bit for each page to allow or disallow accesses to that page.

44. Valid (v) or Invalid (i) Bit In A Page Table Example: address space 14bit (0-16383) program addresses 0--10468; page size ---2 KB;

45. Addresses in pages 0, 1, 2, 3, 4, and 5 are mapped normally through the page table. Any attempt to generate an address in pages 6 or 7, however, finds that the valid-invalid bit is set to invalid, and the computer will trap to the operating system (invalid page reference). • Because the program extends to only address 10468, any reference beyond that address is illegal. However, references to page 5 are classified as valid, so accesses to addresses up to 12287 are valid. Only the addresses from 12288 to16383 are invalid. This problem is a result of the 2 KB page size and reflects the internal fragmentation of paging.

46. page-table length register (PTLR)页表长度寄存器 • Rarely does a process use all its address range. • In fact, many processes use only a small fraction of the address space available to them. • It would be wasteful in these cases to create a page table with entries for every page in the address range. • Most of this table would be unused, but would take up valuable memory space.

47. page-table length register (PTLR) • Some systems provide hardware, in the form of a page-table length register (PTLR), to indicate the size of the page table. • This value is checked against every logical address to verify that the address is in the valid range for the process. • Failure of this test causes an error trap to the operating system.

48. 4. Structure of the Page Table • Hierarchical Paging分级分页 • Hashed Page Tables哈希页表 • Inverted Page Tables倒置页表

49. Hierarchical Page Tables分级页表 • Most modern computer systems support a large logical-address space (232 to 264). In such an environment, the page table itself becomes excessively large.

50. page number page offset p d 20 12 logical-address space 32-bit; page size --- 4 KB (212); each entry--- 4 bytes; Example: page table entries:? ---may consist of up to 1 million (232/212). physical-address space for the page table alone: --- may need up to 4 MB Logical address: Clearly, we would not want to allocate the page table contiguously in main memory.