IEE5011 –Autumn 2013 Memory Systems 3D DRAM using TSV technology

1. IEE5011 –Autumn 2013Memory Systems3D DRAM using TSV technology Hao-Hsuan, Liu Department of Electronics Engineering National Chiao Tung University h1616161@Hotmail.com

2. Outline Introduction 3DTechnology-TSV 3D Processor-DRAM Integration Impacts of TSV in 3D DRAM system Conclusion Reference

3. Introduction-Why we use 3D DRAM? Speed-Memory wall -The growing disparity of speed between CPU and memory Area Power Cost

4. 3Dtechnology (a) 3D packaging technology- Wire bonding, flip-chip bonding, and thinned die to die bonding- Very low interconnect density (b) Transistor build-up 3D technology- High vertical interconnect density- Temperature constraint- Tend to degrade the performance

5. 3D technology (c) Monolithic wafer-level 3D technology- Wafer alignment- Bonding- Thinning- Inter-wafer interconnection- Realized by TSV can have very high density

6. Through-Silicon Via (TSV) Device Process:FEOL(Front-End OF Line)-> BEOL(Back)-> Bonding Via-First:- Before FEOL Via-Middle:- After FEOL, before BEOL Via-Last:- (1) After BEOL- (2) After Bonding[21]

7. Through-Silicon Via (TSV) TSV process flow

8. Through-Silicon Via (TSV) Via-First- Vias are made before CMOS

9. Through-Silicon Via (TSV) Via-Middle- Vias are made between CMOS and BEOL

10. Through-Silicon Via (TSV) Via-Last( After BEOL before Bonding)- Vias are made after BEOL

11. Through-Silicon Via (TSV) Via-Last( After Bonding)- Vias are made after Bonding

12. 3D DRAM Integration Processor consume more energy and generate more heat Stacking a single processor with multiple DRAM dies Processor locates closest to the heat sink

13. 3D DRAM Integration 3D Process-DRAM integrated system architecture

14. 3D DRAM Integration Clearly, through-DRAM TSVs will- Impact the 3D DRAM design- Degrade DRAM storage capacity- Power consumption How to design the TSVs placement?

15. 3D DRAM Integration Proposed design to allocate through-DRAM TSVs

16. 3D DRAM Integration Signal TSVs- minimum allowable TSV size- Tend to occupy a very small area- At the center of DRAM dies Power TSVs- Much bigger impact and design trade-offs- Power consumption overheadReduce the resistance of power TSVs Increase size

17. 3D DRAM Integration Propose to arrange a regular power TSV network around those DRAM sub-arrays

18. Impacts of TSV in 3D DRAM system Impacts of the size of each power TSV

19. Impacts of TSV in 3D DRAM system Impacts of the DRAM Sub-array Size

20. Impacts of TSV in 3D DRAM system Impacts of the DRAM substrate thickness

21. Impacts of TSV in 3D DRAM system Impacts of the contact resistance

22. Conclusion 3D DRAM integration drive innovational changes in performance, power, and cost. Through-silicon-via(TSV) is widely used in the 3D technology, and its parameter will impact the performance and power in 3D system A simple method to allocate power and signal TSVs lead to simply consider the trade-offs.

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26. Thanks for your attention!