Tackling circuit complexity (2)

1. Lecture 6.5 Paolo PRINETTO Politecnico di Torino (Italy)University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu www.testgroup.polito.it Tackling circuit complexity (2)

2. Goal • This lecture is the latter part of a group of 2 lectures aiming at presenting methods used in manual combinational synthesis to overcome the limitations of the purely manual approach presented in lectures 6.1-6.3

3. Prerequisites • Lectures 5.1 and 6.4

4. Homework • Students are warmly encouraged to solve the proposed exercises

5. Further readings • No particular suggestion

6. Outline • Partitioning based techniques • RT level minimizations • Synthesis by iterating basic cells

7. Partitioning-bases techniques • The system is first partitioned in functional blocks • Each functional block is then implemented resorting to one of the above mentioned approaches • The system is eventually designed simply assembling the functional blocks.

8. Partitioning-bases techniques • The system is first partitioned in functional blocks • Each functional block is then implemented resorting to one of the above mentioned approaches • The system is eventually designed simply assembling the functional blocks. This step is iterated until each functional block is implemented resorting to elements that are considered to be “basic” or “elementary” for the target design

9. RT Level Synthesis • A peculiar case is the one in which the “elementary blocks” are the RT level combinational blocks presented in lecture 5.2.

10. User'sRequirements RT Level Synthesis system RT logic Impl behavior structure physical

11. RT level synthesis • Approaches to manual RT level synthesis can be clustered in 2 major classes: • intuitive • systematic(from VHDL RT descriptions) (presented in module 12).

12. Intuitive approach • The intuitive approach will be presented resorting to a couple of examples.

13. |X| Module generator • Design a circuit which, getting in input a number X of n bits, represented according to the 2’complement notation, provides in output the value: • Y = |X|.

14. |X| Module generator • Design a circuit which, getting in input a number X of n bits, represented according to the 2’complement notation, provides in output the value: • Y = |X|. X < 0  Y = | X | =  X X  0  Y = | X | = + X

15. |X| X X 0 1 X < 0  Y = | X | =  X X  0  Y = | X | = + X Y

16. |X| X 2’s compl. X 0 1 X < 0  Y = | X | =  X X  0  Y = | X | = + X Y

17. |X| X 0 2’s compl. < X 0 1 X < 0 Y = | X | =  X X  0 Y = | X | = + X Y

18. Iteration • The process is iterated until all the functional blocks the system has been partitioned in are “elementary”, i.e., can be directly implemented by one of the components present in the target library.

19. Iteration • The process is iterated until all the functional blocks the system has been partitioned in are “elementary”, i.e., can be directly implemented by one of components present in the target library. • Let’s assume the target library be the RT level combinational blocks presented in lecture 5.1

20. |X| Comparator X 0 2’s compl. < X 0 1 Y

21. |X| X 0 2’s compl. < X 0 1 Multiplexer Y

22. |X| X 0 2’s compl. < X 0 1 Can be implemented in several ways Y

23.  X = 0  X 2’s compl.

24.  X = 0  X 0 X 0 2’s compl. ADD/~SUB Adder / Subtracter

25.  X = 1’s_compl(X) + 1 2’s compl.

26.  X = 1’s_compl(X) + 1 1’s compl. 2’s compl. +1

27. 1’s compl.

28. |X| 1 +1

29. |X| Alternative implementation • Design a circuit which, getting in input a number X of n bits, represented according to the 2’complement notation, provides in output the value: • Y = |X|. X < 0  Y = | X | =  X = X’ + 1 X  0  Y = | X | = + X = X + 0

30. |X| X < 0  Y = | X | =  X = X’ + 1 X  0  Y = | X | = + X = X + 0 Y

31. |X| X X’ 0 1 X < 0  Y = | X | =  X = X’ + 1 X  0  Y = | X | = + X = X + 0 Y

32. |X| X 0 1 X’ 0 1 0 1 X < 0  Y = | X | =  X = X’ + 1 X  0  Y = | X | = + X = X + 0 Y

33. |X| X 0 1 X’ 0 1 0 1 X < 0  Y = | X | =  X = X’ + 1 X  0  Y = | X | = + X = X + 0 Y

34. |X| X 0 0 1 X’ < 0 1 0 1 X < 0 Y = | X | =  X = X’ + 1 X  0 Y = | X | = + X = X + 0 Y

35.  Programmable Divider • Design a circuit which, getting in input: • An 8-bit number X coded 2C • A 2-bit number D coded 2C • provides on the output Y (coded 2C) the value Y = X / D

36.  Solution • The divider D can get the following 4 values, only: • D=2 Y = X/2 • D=1 Y = X • D=0 error • D=1 Y = X

37.  X divider / complementer don’t care X/2 X X 10 11 00 01 D 0 = Y ERR

38.  X divider / complementer X/2 X X X 2’s compl. X / 2 X X X/2

39.  / 2

40.  X 2’s compl. X / 2 don’t care X/2 X X 11 00 01 10 D Y

41.  Question • How many bits are needed to properly represent Y?

42.  Answer • D = 1  Y = X • Thus, representing Y requires one bit more than representing X.

43. Outline • Partitioning based techniques • RT level minimizations • Synthesis by iterating basic cells

44. Hints • At the end of an intuitive RT level synthesis, it’s highly recommended to perform an optimization step aiming at locally minimizing the Functional Blocks.

45. Graphic notations U A op U = A1op A2 op … op An where op = and, or, xor, nand, nor, exnor

46. Graphic notations U A op U = A1op A2 op … op An A U op Ui = Aiop B B where op = and, or, xor, nand, nor, exnor

47. Graphic notations U A op U = A1op A2 op … op An A U op Ui = Aiop B B A U op Ui = Aiop Bi B where op = and, or, xor, nand, nor, exnor

48. Some optimizations...

49. 1 0 select 1 0

50. 1 0 select 1 0 select