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Thermal Design And Analysis of High Power Electronic Boards. J. Collado CHT, April 13, 2000. Thermal Requirements. Maximum junction temperatures and dereating criteria Thermal environments in which the equipment is required to operate Ambient temperature Altitude/Pressure

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Presentation Transcript
thermal requirements
Thermal Requirements
  • Maximum junction temperatures and dereating criteria
  • Thermal environments in which the equipment is required to operate
    • Ambient temperature
    • Altitude/Pressure
    • Thermal radiation environment
    • Solar heat loads
    • Air velocity
    • Government specifications
    • Mission profile and duration
  • Design constraints
    • Noise and vibration limits
    • Maximum allowable air exhaust temperature
    • Size limit
    • Weight limits
governing equations

A

T1

T2

q-------> o-----/\/\/\-----o

R1-2

L

Governing Equations

q = -kA dT/dx

Integrated Equation Forms:

q = (kA/L)(T1-T2)

q = G(T1-T2) = (T1-T2)/ q1-2

where:

q1-2 = 1/G = R = L/kA

or

q1-2 = 1/G = R = LN(d2/d1)/2pLk (Radial)

k = material thermal conductivity (W/in-°C)

G = thermal conductance (W/°C)

d = equivalent diameter

Fourier’s Law of Heat Conduction

thermal resistance to conduction
Thermal Resistance to Conduction
  • Thermal Resistance, R (°C/Watt)
  • R=1/G (the inverse of thermal conductance, G)
  • R1-2 is the resistance from point 1 to point 2
  • For electronic components: R1-2 = q1-2
  • Rj-c= qj-c Junction to Case Thermal Resistance
  • Rc-b= qc-b Case to Board Thermal Resistance
  • Rj-b= qj-b Junction to Board Thermal Resistance
  • Rj-b= Rj-c+ Rc-b= qj-b = qj-c + qc-b
thermal resistance equations cont
Thermal Resistance Equations (Cont.)
  • Junction Temperature Calculation
  • Thermal Via Holes Thermal Resistance

r2

r1 = rOUT

-

ln(

r

r

)

r1

q

=

2

1

1

p

2

L1K

rin = r Cu after plating

rout

L2

q

=

p

2

-

2

2

K

(

r

r

)

PWB

L2

out

in

4

rin

typical assumptions
Typical Assumptions
  • Component case is isothermal
  • Board bottom is isothermal under the part
  • Heat sink is isothermal under the part
  • No convection or radiation heat transfer
  • Extra footprint area for PWB calculations
    • lead vias are defaulted to be under the part
type of electronic packages
Type of Electronic Packages
  • Through Hole
    • Part leads pass through a circuit board
    • e.g., DIPs, Axial Diodes, Transistors, PGAs
  • Surface Mount Devices (SMD)
    • Parts leads stop at the circuit board surface
    • e.g., SOICs, PLCCs, QFP, SOTs
    • Parts leads stop at the circuit board surface
      • e.g., SOICs, PLCCs, QFP, SOTs
effects of thermal vias on pwb operating temperature
Effects of Thermal Vias on PWB Operating Temperature

Board With No Thermal Vias

Board With Thermal Vias