Multiplexors

1. Lecture 6 Multiplexors Sequential Circuits and Finite State Machines Prof. Sin-Min Lee Department of Computer Science

3. Two-Level NAND Gate Implementation Example 1

4. Two-Level NAND Gate Implementation Example 1

6. Design Procedure • Determine the required number of inputs and outputs and assign letter symbols to them. • Derive the truth table that defines the required relationship between inputs and outputs. • Obtain the Boolean function. • Draw the logic diagram. • Verify the correctness of the design.

7. Example • Design a circuit that converts a BCD codeword to its corresponding excess-3 codeword. We need 4 input variables and 4 output variables. Let us designate the 4 input binary variables by the symbols A, B, and C and D, and the four output variables by w, x, y, and z. The truth table relating the input and output variables is shown below:

8. Note that the outputs for inputs 1010 through 1111 are don't care.

11. Two-Lvel NOR Gate Implementation Example 2 e

17. Multiplexers • A combinational circuit that selects info from one of many input lines and directs it to the output line. • The selection of the input line is controlled by input variables called selection inputs. • They are commonly abbreviated as “MUX”.

20. Combinational circuit implementation using MUX • We can use Multiplexers to express Boolean functions also. • Expressing Boolean functions as MUXs is more efficient than as decoders. • First n-1 variables of the function used as selection inputs; last variable used as data inputs. • If last variable is called Z, then each data input has to be Z, Z’, 0, or 1.

23. Karnaugh Map Method of Multiplexer Implementation Consider the function: A is taken to be the data variable and B,C to be the select variables.

24. Example of MUX combo circuit • F(X,Y,Z) = Sm(1,2,6,7)

26. Sequential Logic • Combinatorial components: the output values are computed only from their present input values. • Sequential components: their output values are computed using both the present and past input values. • Sequential circuits can contain only a finite number of states finite state machines • Synchronous and Asynchronous

28. Sequential Circuits • Contains Memory Elements • Asynchronous sequential circuits change their state and output values when input changes • Synchronous sequential circuits change their output values at fixed points of time, which are specified by the rising or falling edge of a clock signal • Clock period is the time between successive transitions in the same direction • Active high – state changes occur at the clock’s rising edge( on higher voltage) • Active low – state changes occur at the clock’s falling edge( on lower voltage)

29. 4 Basic types of Flip-Flops • SR, JK, D, and T • JK ff has 2 inputs, J and K need to be asserted at the same time to change the state • D ff has 1 input D (DATA), which sets the ff when D = 1 and resets it when D = 0 • T ff has1 input T (Toggle), which forces the ff to change states when T = 1 • SR ff has 2 inputs, S (set) and R (reset) that set or reset the output Q when asserted

32. Gated D-Latch • Ensures S and R inputs never equal to 1 at the same time • Useful in control application where setting or resetting a flag to some condition is needed • Stores bits of information • Constructed from a gated SR latch and a Data latch

34. J Q CLK To Be Designed D Q’ K Recap - Sequential Systems • Example: • Design a D FF with a JK FF and AND, OR, NOT gates:

35. 0 1 Sequential Systems - Cont. D(t) 0- 1--1 -0JK

36. D - - 1 0 0 1 - - Q K = D’ J = D D • D J Q CLK Q Q’ K Sequential Systems - Cont.

37. Analysis of Sequential Systems • Goal: • Decide the timing and functional behavior from the implementation of a sequential system composed of FFs and logic gates • Types: • Functional analysis • Timing analysis

38. Characteristic Equation of FFs

39. D Flip-Flop Q+ = Next State Characteristics : Synchronous Avoids the instability of RS flip-flop Retains its last input value To set the ff, place 1 on D input and pause the CK input To reset, place 1 on D input and pause the CK input

40. T Flip-Flop T = 1 force the state change T = 0 state remain the same

41. JK – Flip Flop J – Set K – Reset J = K = 0 – output does not change J = K = 1 – invert the outputs

42. Clocked JK – Flip Flop

43. D and JK Flip-Flop

44. X Y 2 – TO –1 MUX F Z

45. T CLK Q1

46. T CLK Q1

47. J K CLK Q1

48. How to use JK to implement D Flip-Flop D ff’s property: When in = 0, the out(Q+) = 0. When in = 1, the out(Q+) is 1   invert K   invert K D

49. How to use JK to implement T Flip-Flop T ff’s property: When in = 0, the out(Q+) = no change When in = 1, the out(Q+) is = complement  No change  State change T

50. How to use D to implement JK Flip-Flop (Q ) = no state change (Q’) = state change D = JQ’ + K’Q