1 / 28

Synthesizing and Testing LEON on ADM-XRC

This presentation by Anup Gangwar from the Embedded Systems Group at IIT Delhi details the process of synthesizing and testing the LEON processor on the ADM-XRC board. It explores the architecture of both the LEON processor and the ADM-XRC board, discusses the challenges faced during interfacing with ZBT SRAM, and highlights the significance of proper methodology in prototyping and testing. Furthermore, it shares insights on the development toolkit, the booting process, and future directions for research. Acknowledgements are also provided to contributors and resources used throughout the project.

wade-durham
Download Presentation

Synthesizing and Testing LEON on ADM-XRC

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Synthesizing and Testing LEON on ADM-XRC Anup Gangwar Embedded Systems Group Department of Computer Science & Engineering IIT Delhi

  2. Presentation Outline • Introduction • LEON processor architecture and development toolkit • ADM-XRC board architecture • Why it took so long? • Interfacing ZBT SRAM • Building external hardware interface • Booting LEON • From here • Acknowledgements

  3. Introduction • What is LEON? • A Sparc V8 compliant soft processor core • No support for paging • Has been synthesized and tested on many FPGA platforms • Mainly written by Jiri Gaisler at European Space Agency • Supporting toolkit (compiler, assembler, simulator) available • RTEMS successfully ported to LEON with support for n/w interface • How is this relevant to our work? • Real performance/cost nos. give valuable feedback to our tools • Prototyping adds credibility to our work • System design experience lets us identify new problems • Working demonstrations help motivate new people

  4. Presentation Outline • Introduction • LEON processor architecture and development toolkit • ADM-XRC board architecture • Why it took so long? • Interfacing ZBT SRAM • Building external hardware interface • Booting LEON • From here • Acknowledgements

  5. The LEON Processor Architecture FPU LEON IU PCI Co-Proc AHB Controller I-Cache D-Cache User I/O AMBA AHB AHB/APB Bridge Timers/UARTs/ I/O Ctrl/IRQ Ctrl Memory Controller AMBA APB PROM/RAM/ I/O

  6. LEON Development Tools Suite C-Code RTEMS Library GCC - Ported GNU Cross Compiler System TSIM - LEON Functional Simulator Modify C Code N Performance and Functionality Okay? Y ObjCopy - Ported GNU Binutils System SREC File - Containing Stripped Relocatable Symbols

  7. Motorola S-Records Format • S<type><length><address><data....><checksum> type => in the range [1-7] length => length of (address + data + checksum) in hex address => [4-6] hex characters (16-32 bit address) data => each hex pair represents one memory byte S3 => data record with 32-bit addresses S7 => Ending record for S3 records, address is the jump address for starting execution

  8. Presentation Outline • Introduction • LEON processor architecture and development toolkit • ADM-XRC board architecture • Why it took so long? • Interfacing ZBT SRAM • Building external hardware interface • Booting LEON • From here • Acknowledgements

  9. ADM-XRC Architecture RAM0 RAM1 RAM2 RAM3 Clock Gen. XCV800-BG560-6 34 I/O pins on SCSI-II style connector PLX 9080 ADM-XRC HOST PCI Bus

  10. ADM-XRC Software API • Supported platforms are GNU-Linux and Windows NT • API Supports: • Functions for configuring the Virtex device over PCI • DMA mode for data transfer from/to PLX-9080 • Both master/slave mode supported for PLX-9080 • Examples demonstrate: • Simple PCI interface • RAM interface with address space segregation • DMA Master and slave interfaces • External I/O interfaces

  11. Presentation Outline • Introduction • LEON processor architecture and development toolkit • ADM-XRC board architecture • Why it took so long? • Interfacing ZBT SRAM • Building external hardware interface • Booting LEON • From here • Acknowledgements

  12. Why it took so long? • Inability to comprehend the problem properly • Improper documentation of ZBT memory interface • Improper methodology for prototyping and testing • Synthesis being used as testing vehicle which is incorrect • After thorough simulation synthesis should be a one-shot process unless the synthesis tools are buggy • External H/W interface was incorrect • Unnecessary additional logic inversion • Position of Rx and Tx in 9-pin and 25-pin connectors is interchanged • LEON and memory address lines were not properly mapped • LEON address lines select individual bytes! • Memory word is 32 bits here hence LEON A[1:0] need to be left free

  13. Presentation Outline • Introduction • LEON processor architecture and development toolkit • ADM-XRC board architecture • Why it took so long? • Interfacing ZBT SRAM • Building external hardware interface • Booting LEON • From here • Acknowledgements

  14. Galvantech ZBT SRAM Interface Signals LEGEND Galvantech 512K x 36bits CLK CKE# CE# OE# R/W# ADV/LD# BW[a-d]# Address Data

  15. ZBT SRAM Read Timing Diagram CLK OE# ADV/LD# DON’T CARE R/W# DON’T CARE Address Data

  16. ZBT SRAM Write Timing Diagram CLK DON’T CARE OE# ADV/LD# DON’T CARE R/W# DON’T CARE Address Data

  17. LEON SRAM Read Timing Diagram CLK RAMOEN RAMSN Address Data

  18. LEON SRAM Write Timing Diagram CLK RWEN RAMSN Address Data

  19. Presentation Outline • Introduction • LEON processor architecture and development toolkit • ADM-XRC board architecture • Why it took so long? • Interfacing memory • Building external hardware interface • Booting LEON • From here • Acknowledgements

  20. External Hardware Interface • Why is external hardware circuitry needed? • Virtex SelectIOTM supports PCI3.3, LVTTL etc. logic levels • RS-232C voltage conversion required for TxD and RxD pins • Choices for interface chips • Motorola MC1488/1489 • Require dual supply, +5V, ±12V • Better noise immunity but bigger circuitry • LVTTL to RS232C and RS232C to LVTTL requires two chips • Maxim Max232 • Single power supply, +5V • Each chip contains two RS232C to LVTTL and two LVTTL to RS232C converters • Lesser noise immunity but more compact circuitry

  21. H/W Interface Board Layout MAX 232 (RS-232C voltage level converters) Host serial port connections 15 I/O connections from ADM-XRC mapped here Supporting Circuitry Power Supply Probe Points Power LED Error LED

  22. Presentation Outline • Introduction • LEON processor architecture and development toolkit • ADM-XRC board architecture • Why it took so long? • Interfacing memory • Building external hardware interface • Booting LEON • From here • Acknowledgements

  23. Boot Configuration ADM-XRC Onboard ZBT SSRAMs used as LEON RAMs RAM0 RAM1 RAM2 RAM3 H/W Interface Board Xilinx Virtex XCV800-BG560-6 (virtex_2k_2k_blockprom) Errorn, Resetn, UART1 and UART2 ports mapped to 34 I/O pins for interface BlockRAMs containing boot-prom, Register Files, Caches etc (These are instantiated not inferred) PLX9080 Host PCI Bus (Used for configuring Virtex) Host Serial Port - 1 (stdin/stdout) Host Serial Port - 2 (UNIX File Descriptors 2 & 3) Host Computer

  24. Presentation Outline • Introduction • LEON processor architecture and development toolkit • ADM-XRC board architecture • Why it took so long? • Interfacing memory • Building external hardware interface • Booting LEON • From here • Acknowledgements

  25. From Here: • Small Scope Projects: • Try various hardware synthesis configurations for LEON • Build S/W and H/W estimator models for LEON • Medium Scope Projects: • Build a host of coprocessors for LEON • Test some PCI cards with LEON-PCI • Port some real applications to LEON-RTEMS • Build Ethernet interface for LEON (RTEMS support is already present) • Large Scope Projects: • Extend LEON configuration for multiprocessors • Customize RTEMS for a particular application/LEON configuration

  26. Presentation Outline • Introduction • LEON processor architecture and development toolkit • ADM-XRC board architecture • Why it took so long? • Interfacing memory • Building external hardware interface • Booting LEON • From here • Acknowledgements

  27. Acknowledgements • Main ideas, motivation and support • Prof. M. Balakrishnan and Prof. Anshul Kumar • Co-Proc interface, Local Bus interface, Bugs in memory interface • Amarjeet Singh • Debugging, Memory interface, External RS-232C hardware interface circuitry • Amit Aggarwal, Puneet Wadhawan

  28. Thank You

More Related