robust window based multi node technology independent logic minimization n.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
Robust Window-based Multi-node Technology-Independent Logic Minimization PowerPoint Presentation
Download Presentation
Robust Window-based Multi-node Technology-Independent Logic Minimization

Loading in 2 Seconds...

play fullscreen
1 / 39

Robust Window-based Multi-node Technology-Independent Logic Minimization - PowerPoint PPT Presentation


  • 106 Views
  • Uploaded on

Robust Window-based Multi-node Technology-Independent Logic Minimization. Jeff L.Cobb W Kanupriya Gulati D Sunil P. Khatri D. W Texas Instruments, Inc. D Dept. of ECE, Texas A&M University. Overview Introduction Background Previous work Approach Experimental results Conclusions.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

Robust Window-based Multi-node Technology-Independent Logic Minimization


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
robust window based multi node technology independent logic minimization

Robust Window-based Multi-node Technology-Independent Logic Minimization

Jeff L.Cobb W

Kanupriya Gulati D

Sunil P. Khatri D

W Texas Instruments, Inc.

D Dept. of ECE, Texas A&M University

slide2

Overview

Introduction

Background

Previous work

Approach

Experimental results

Conclusions

slide3

Introduction

VLSI design flow

  • HDL (Verilog, VHDL)
  • Logic optimization
  • Physical design
slide4

Introduction

  • Purpose of logic optimization
    • Reduce area
    • Reduce power
    • Reduce delay
  • Logic optimization
    • Technology-independent optimization
      • Goal: reduce literal count
    • Technology-dependent optimization
slide5

Background

  • Don’t Cares
    • Logic function allowed to have 0 or 1 as possible output for a given input

ODC SDC

    • XDC: External don’t cares given
slide6

Background

  • Don’t Cares
    • Computed for one node at a time
    • Cannot capture multi-node flexibility

xy (x+y) = xy(xy) + (x+y)(x+y) = xy+xy = x y

  • Goal: multi-node logic minimization
    • Yields a Boolean relation
    • Need to determinize this relation for solution
slide7

Background

  • Boolean relations
    • Can express more than one allowed output vector for a single input vector
    • Don’t cares only express flexibility for a single output
slide9

Problem Definition

  • Implement dual-node Boolean relation-based multi-level logic minimization technique
  • Goals:
    • Method must scale to large designs
    • Compare to best don’t care-based method (single-node)
slide10

Previous Work

  • [CM77] Formulated multi-node minimization problem
    • No results provided
  • [WW94] Multi-node minimization
    • Extremely large runtimes, works on very small designs
  • [MB05] Single node approach, uses windowing and SAT based formulation
    • Used for comparison purposes
  • This work: Efficient choice of nodes, window based, efficient quantification scheduling

10

slide11

Approach

  • Key features
    • Dual node optimization
    • Careful node pair selection
    • Window based optimization technique
    • Early quantification for efficiency
slide13

Node Pair Selection

  • Node Pair Selection
slide16

Node Pair Selection

  • Compute common input ratio
  • Compute common output ratio
  • Select node pairs that satisfy
slide23

Endgame

  • Call BREL (a Boolean relation minimizer) to minimize
    • Returns new nodes and
  • Graft new nodes into
  • Delete original nodes
  • ,
slide24

BREL

  • BREL is a heuristic Boolean relation solver
    • Solving a Boolean relation
      • Same as minimum cost determinization of the relation (i.e. finding the lowest cost function which is contained in the relation)
    • Branch and bound approach
slide25

Experimental Results

  • Implemented in SIS
  • Uses CUDD ROBDD Package
  • 15 benchmark circuits from mcnc91, itc99
  • Metric for quality: literal count
  • Preprocessing steps:
      • Removes constant-valued nodes
      • Removes nodes that do not fanout
      • Merges functionally identical nodes
slide26

Experimental Results

  • Parameter selection
    • 4 parameters to node selection algorithm
    • Goal: Find “golden” values
slide28

Experimental Results

  • Parameters:
    • : Window size
    • : Partners for
slide31

Experimental Results

  • “Golden” parameter values:
    • Can be modified to balance quality/runtime
slide32

Experimental Results

  • Compared versus
  • 12% lit. improvement
  • 38x runtime increase
    • But runtimes are
    • still within 3-4 min
  • Low memory (#BDD
  • nodes)
  • High gain (number of
  • node pairs which give
  • an improvement)
slide33

Experimental Results

  • Run after
  • 13% lit. improvement
  • Both use 2x2 windows
slide34

Experimental Results

  • Limit subnetwork size τ
slide35

Conclusions

  • 12% less literals than best DC approach
  • Runtimes under 4 minutes for largest network
  • Low memory usage
  • Further reduce literals by 13% after running best DC approach
  • Future Work
    • Consider 3+ nodes in relation
    • SAT-based relation construction
    • Alternative to BREL